Clock Polarity - HP 3563A Operating Manual

(
Data
1
Pod
Data
Clock
Qualifiers
1
CHAN
CLOCK
CHAN 2
CLOCK
Figure 1 3-21. Selecting Channel Clocks for Sample Clock

Clock Polarity

You may define the active transition on most of the system clocks. The positive selection ( +
the low-to-high transition active and the negative selection (
active. Data clock polarity is selected in the DATA CLOCK menu. The polarity of the sample clock
is
determined by the selection of sample clock:
•
If
the sample clock is the Pod Q clock, the polarity is selected in the sample clock menu.
•
If
the sample clock is one of the two channel clocks, the polarity is determined by the
configuration of the corresponding data clock.
•
If
the sample clock is the external sample signal (a BNC connector on the rear panel) the
polarity is not selectable; its active transition
i-
!
Sample includes this data if 2
sample clock is CHAN
i
1
Channel
Channel data
.1---
Sample includes this data if
I
sample clock is CHAN
1
Clock Qualifier
Clock Qualifier
Channel
Channel
is
Connecting the Sample Clock
----4
CLOCK
1
2
data Channel data
-i
1
CLOCK
2 1
Clock Qualifier
Channel
-
) .makes the high-to-low transition
always low-to-high.
a
Digit l Connections
2
Channel data
I
2
Clock Qualifier
Channel
)
makes
1 3-21