Digital Interface - Matrox Corona Installation And Hardware Reference

PSG
Phase-locked loop
The programmable synchronization generator (PSG) allows
Matrox Corona to adapt to many video standards. It is required
for asynchronous reset modes, progressive scan acquisition,
and for management of all other non-standard timings. The
PSG also generates synchronization signals when Matrox
Corona operates in master mode (discussed later).
Using Matrox Intellicam, you can set the active video region,
the sampling clock, and all the other parameters related to the
timing of the video signal (that is, standard and non-standard
video) in your DCF file.
Once this is done, some of the video parameters can be changed,
using the MIL-Lite MdigControl() command.
The high-performance, low-jitter phase-locked loop (PLL) uses
frequency synthesis techniques to generate the clock signal,
when necessary.
The PLL can use the following sources as a reference:
The on-board crystal oscillator.
The horizontal video synchronization signal supplied by the
video source (line-locked mode).
When in line-locked mode and accepting a composite video
signal, the PLL can synchronize to either serrated or block
vertical synchronization signals.
The clock signal supplied by the video source (to generate a
different clock).
When the input source supplies a sampling clock that does not
require adjustment, the PLL is bypassed to avoid adding jitter
to the supplied clock.

Digital interface

The digital interface captures TTL level digital video at up to
24 bits per pixel. It is designed to receive data through the
companion digital-input board (or from a TTL digital video
source), and to feed data to a Matrox Genesis main or processor
board.
Acquisition section 53