Gpio 8-11 (Cn41); Miscellaneous (Cn43) - ADLINK Technology LEC-BASE MINI Technical Reference

3.18 GPIO 8-11 (CN41)

Table 3-25 lists the pin signals of the General Purpose IO 8-11 header, which provides 10 pins in
2 rows, odd/even pin sequence (1, 2), and 2.54mm pitch.
Pin #
1 +V5P0A
2 CN_GPIO8 (connected to SMARC pin P116)
3 +V3P3S
4 CN_GPIO9 (connected to SMARC pin P117)
5 GND
6 CN_GPIO10 (connected to SMARC pin P118)
7 GND
8 CN_GPIO11 (connected to SMARC pin P119)
9 GND
10 GND
NOTE: These GPIOs are shared function pins. See SMARC Specification 1.1. Shaded table
cells denote power or ground

3.19 Miscellaneous (CN43)

Table 3-26 lists the pin signals of the Miscellaneous header, which provides 10 pins in 2 rows,
odd/even pin sequence (1, 2), and 2.54mm pitch.
Pin #
1 GND
2 BATLOW#
3 GND
4 BB_STBY#
5 GND
6 CHARGER_PRSNT#
7 GND
8 CHARGING#
9 GND
10 LID#
NOTE: Shaded table cells denote power or ground. The # symbol indicates the signal is Active
Low.
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Table 3-25: General Purpose IO 8-11 (CN41)
Table 3-26: Miscellaneous (CN43)
Signal
Signal
Interfaces