Gpio 4-7 (Cn39) - ADLINK Technology LEC-BASE MINI Technical Reference

Table 3-23: Alternate Function Block Interface Pin Signals (CN37) (Continued)
28 GND
29 GND
30 AFB_DIFF4+ (connected to SMARC pin S74)
31 AFB8_PTIO (connected to SMARC pin S55)
32 AFB_DIFF4- (connected to SMARC pin S75)
33 AFB9_PTIO (connected to SMARC pin S56)
34 GND
NOTE: The shaded table cells denote power or ground.

3.17 GPIO 4-7 (CN39)

Table 3-24 lists the pin signals of the General Purpose IO 4-7 header, which provides 10 pins in
2 rows, odd/even pin sequence (1, 2), and 2.54mm pitch.
Pin #
1 +V5P0A
2 CN_GPIO4 (connected to SMARC pin P112)
3 +V3P3S
4 CN_GPIO5 (connected to SMARC pin P113)
5 GND
6 CN_GPIO6 (connected to SMARC pin P114)
7 GND
8 CN_GPIO7 (connected to SMARC pin P115)
9 GND
10 GND
NOTE: These GPIOs are shared function pins. See SMARC Specification 1.1. Shaded table
cells denote power or ground
Interfaces
Table 3-24: General Purpose IO 4-7 (CN39)
GND
GND
SATA1_RXP on Intel SOC for
SATA high-speed, positive signal
of pair
Reserved
SATA1_RXN on Intel SOC for
SATA high-speed, negative signal
of pair
Reserved
GND
Signal
LEC-BASE MINI
33