Interface Timing; Timing Characteristics - Advantech IDK-2110 Series User Manual

B7
B6
B5
B4
B3
B2
B1
B0
RxCLKIN
DE
VS
HS
Note: Output signals from any system shall be low or Hi-Z state when VDD is off.
3.4

Interface Timing

3.4.1

Timing Characteristics

Table 3.2: Timing Characteristics
Signal
Clock Timing
Vsync Timing
Hsync Timing
Note Frame rate is 60 Hz.
Note DE mode.
Note Typical value refer to VESA STANDARD
IDK-2110 User Manual
Blue Data 7
Blue Data 6
Blue Data 5
Blue Data 4
Blue Data 3
Blue Data 2
Blue Data 1
Blue Data 0
LVDS Data Clock
Data Enable Signal
Vertical Synchronous
Signal
Horizontal Synchro-
nous Signal
Parameter
Clock frequency
Period
Vertical
Active
Section
Blanking
Period
Horizontal
Active
Section
Blanking
Blue-pixel Data, For 8 bits LVDS input, MSB: B7;
LSB:B0
When the signal is high, the pixel data shall be
valid to be displayed.
Symbol Min.
1/ T 33.6
Clock
T 608
V
T 600
VD
T 8
VB
T 920
H
T 800
HD
T 120
HB
14
Type. Max.
39.8 48.3
628 650
600 600
28 50
1056 1024
800 800
256 440