Interface Timing; Timing Characteristics - Advantech IDK-2115 Series User Manual

B7
B6
B5
B4
B3
B2
B1
B0
RxCLKIN
DE
Note: Output signals from any system should be low or Hi-Z state when VDD is off.
3.4

Interface Timing

3.4.1

Timing Characteristics

The input signal timing specifications are shown as the following table and timing dia-
gram.
Table 3.2: Timing Characteristics
Signal Item
DCLK Pixel Clock
Vertical Total Time
Vertical Address Time T
DE
Horizontal Total Time T
Horizontal Address
Time
Note: Because this module is operated by DE only mode, Hsync and Vsync input
signals should be set to low logic level or ground. Otherwise, this module
would operate abnormally
IDK-2115 User Manual
Blue Data 7
Blue Data 6
Blue Data 5
Blue Data 4
Blue-pixel Data, For 8 bits LVDS input, MSB: B7;
LSB:B0
Blue Data 3
Blue Data 2
Blue Data 1
Blue Data 0
LVDS Data Clock
Data Enable Signal When the signal is high, the pixel data is valid to
be displayed.
Symbol
1/T
C
T
V
VD
H
T
HD
14
Min. Typ. Max.
- 65 80
780 806 1200
768 768 768
1140 1344 1600
1024 1024 1024
Unit Note
MHz -
T -
H
T -
H
T -
C
T -
C