Interface Timing; Timing Characteristics - Advantech IDK-2115 Series User Manual

G7
G6
G5
G4
G3
G2
G1
G0
B7
B6
B5
B4
B3
B2
B1
B0
RxCLKIN
DE
VS
HS
Note: Output signals from any system shall be low or Hi-Z state when VDD is off.
3.4

Interface Timing

3.4.1

Timing Characteristics

Table 3.2: Timing Characteristics
Signal Parameter
Clock Clock frequency
Timing
Vsync Vertical
Timing Section
Hsync Horizontal
Timing Section
Note Frame rate is 60 Hz.
Note DE mode.
Note Typical value refer to VESA STANDARD
IDK-2115 User Manual
Green Data 7
Green Data 6
Green Data 5
Green Data 4
Green-pixel Data, For 8 bits LVDS input, MSB:
G7; LSB:G0
Green Data 3
Green Data 2
Green Data 1
Green Data 0
Blue Data 7
Blue Data 6
Blue Data 5
Blue Data 4
Blue-pixel Data, For 8 bits LVDS input, MSB: B7;
LSB:B0
Blue Data 3
Blue Data 2
Blue Data 1
Blue Data 0
LVDS Data Clock
Data Enable Signal When the signal is high, the pixel data shall be
valid to be displayed.
Vertical Synchronous
Signal
Horizotal Synchronous
Signal
Symbol
1/ T
Clock
Period T
V
Active T
VD
Blanking T
VB
Period T
H
Active T
HD
Blanking T
HB
12
Min. Typ. Max.
50 65 81
776 806 1024
768 768 768
8 38 256
1054 1344 2048
1024 1024 1024
30 320 1024
Unit
MHz
T
Line
T
Clock