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Chapter 3: Testing Logic Analyzer Performance
Test Pod 1 in 600 Mb/s Mode
16950A→Timing/State (Sampling)...
9 In the State Options section, Sampling Options field, select the "600 MHz"
mode. A warning will appear stating that one Pod pair is required for
timetag storage. Select OK.
10 Ensure that the Clk1 mode is set to Rising Edge.
11 In the logic analyzer's Buses/Signals window, unassign all bits.
12 Assign bits 2, 6, 10, and 14 of Pod 1.
13 Ensure that the Pod 1 threshold is set to 1 volt. See page 40.
14 Use the scroll bar at the bottom of the window to scroll to the left (if
scrolling is necessary) and select the Clock Thresholds button. In the Clock
Thresholds window, ensure that the Clk1 threshold is set to Differential.
a Select OK to close the Clock Thresholds window.
Determine and set Eye Finder Position (600 Mb/s mode)
15 Select the Sampling tab.
16 Select the Sampling Positions button.
17 In the Eye Finder window, expand "My Bus 1".
18 If the blue bars are not vertically aligned, align them. See page 44.
19 Grab the blue bar for "My Bus 1" and move it to approximately
-2.9 ns. All blue bars will follow.
20 Run Eye Finder and note the average sampling position chosen by Eye
Finder:______ns. In the following example, the average sampling position
is -2.93 ns. Note that in this step, you place the blue bars in the narrow
window (not the wide window) that appears to the left of zero in the Eye
Finder display. Then run Eye Finder. The position may be different based
on your test setup. Bring stray channels into alignment if necessary. See
54
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