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Chapter 5: Troubleshooting
internal to the FPGAs.
Chip Registers Read/Write Test. The purpose of this test is to verify that each
bit in each register of the Analysis chips can be written with a 1 and 0 and read
back again. The test also verifies that a chip reset sets all registers to their reset
condition (all 0s for most registers).
Analyzer Chip Memory Bus Test. The purpose of this test is to check the
Analysis chip memory busses that go between the Analysis chips and the SDRAM
controller FPGAs.
Comparators Programming Test. The purpose of this test is to verify the
programming path to each of the comparators.
Comparator/DAC Test. This test uses the pod, bonus, and calibration DACs,
the calibration oscillator (implemented in the interface FPGA), the comparators,
the connections between the comparators and the Analysis chips, and the activity
indicators in the Analysis chips. We verify that we can use the DACs to control
the data input to the comparators. We verify that each comparator data channel
produces output. We verify that each comparator output is connected to each
ASIC data input.
Comparator Delay Test. The comparator delay test verifies the integrity of all
the delay line elements for each delay line in the comparators. Each delay line
consists of 11 delay elements. When set for maximum delay, all 11 elements are
connected in series. If any element is faulty, then data will not propagate through
the comparator. If this is the only test failing, then it is almost certainly a bad
comparator.
Comparators V Offset Test. This test will not be executed if any probes are
attached to any of the probe cables. This test verifies that the V Offset (offset
null) taps for each data channel of each comparator can be independently
programmed and that each tap has the expected effect on the V Offset
adjustment. The tap settings are programmable inside each comparator chip. If
this is the only test failing, then it is almost certain that is a bad comparator.
System Clocks (J/K/L/M/Psync) Test. The purpose of this test is to verify that
the four clocks (J/K/L/M) are functional between the master board and all
Analysis chips, and that the two Psync lines (A/B) are functional between the
master board's Analysis chips and all Analysis chips in the module. This test
verifies that the four clock lines (J/K/L/M) are driven from the master board and
can be received by all Analysis chips, and that the Psync lines can be driven by
each master chip on the master board and received by all other Analysis chips in
the module.
System Backplane Clock Test. The purpose of this test is to verify the system
backplane 100 MHz clock is functional to each Analysis chip and running at the
correct frequency. This test also verifies that the PLL in each chip can be
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