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Chapter 5: Troubleshooting
EEPROM Test. The purpose of this test is to verify:
The address and data paths to the EEPROM
That each cell in the EEPROM can be programmed high and low
That individual locations can be independently addressed
The EEPROM can be block erased
ADC Test. The purpose of this test is to verify that the three test voltages can be
properly read from the Analog to Digital converter. This verifies that the ADC
reference voltages are properly connected and that the correct data can be read
from the device.
Probe ID Read Test. The purpose of this test is to verify that the Probe ID
values can be correctly read and to verify the functionality of the Digital to
Analog Converter by testing the two Probe ID DAC outputs at various voltage
levels.
Memory Data Bus Test. The purpose of this test is to check out the basic write/
read access of the SDRAM from the module backplane bus. This test verifies the
operation of the SDRAM data bus as well as some of the operation of the SDRAM
control and address busses. This is the first test that accesses the SDRAM
acquisition memory using the SDRAM controller FPGAs.
Memory Address Bus Test. The purpose of this test is to completely verify the
SDRAM address lines (DDR_xxx_PORT_x_DDR and DDR_xxx_PORT_x_BA).
HW Assisted Memory Cell Test. The purpose of this test is to fully check all of
the SDRAM memory locations in all SDRAM memory devices.
Memory Unload Modes Test. The purpose of this test is to check the various
modes of unloading data from the SDRAM memories. These modes are setup by
writing to registers in the SDRAM controller FPGAs. The SDRAM controller
FPGAs sequence the data and perform data decoding based on the mode.
Memory DMA Unload Test. The purpose of this test is to check the various
modes of unloading data from the SDRAM memories using DMA backplane
transfers. This test is essentially the same as the unloadTest except that DMA
backplane transfers are used to read the data from the board.
HW Accelerated Memory Search Test. This test verifies the FPGA based HW
Accelerated Search function. It has two modes:
1. A quick test that focuses on the AND functions in the memory controller
FPGAs that combine the pattern detected outputs from each FPGA and sends
the result to the FPGAs on the master board via the 2x15 clock/cal signal cables
(see page 124 for 2x15 cable part number). In doing this, it checks the basic
PATTERN search capability of the FPGAs. This is the default mode.
2. An extended test that also checks each search mode of the FPGAs (NOT
Pattern, Entering, Exiting, and Transition, in non-interleaved, interleaved tags,
and half channel modes). No additional circuitry is tested, except for logic
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