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PA-W1400
(1) outline of electrical section
The CPU of this model is M50734SP, which is a C-MOS 8-bit single-
chip microcomputer composed of the M50740 CPU core, clocked
serial I/O, A-D convertor, watch dog timer, and 35 lines of parallel /O.
The CPU has iMB direct access memory space and 35 lines of VO
ports. The gate array (G.A.) UPD65027G is provided in the peripheral
of the CPU, composing the bank circuit.
ROM's of 4MB and 256KB, dynamic RAM of 256KB, and static RAM
(1051832) of 256KB are used to store all control programs and data
for spell check, thesaurus, and grammar.
The CR (carrier) motor, WH (wheel) motor, and KEY are controlled
through the CPU I/O ports.
The RB (ribbon) motor, PF (paper feed) motor, HAMMER-solenoid,
LCD, and FDD (floppy disk drive) are controlled through the exten-
sion ports of the gate array.
The CPU pin configuration and block diagram are shown below:
CPU block diagram
XIN XQUT &
Program
counter
PCH (8)
Program
counter
Pol (8)
VREF
'Accumulator
AB)
xe)
P4 & analog
NO port
Input AN
u0(8)
sciK
isto
ADB(8)
P3(6)
'Address bus A
'Address &
data bus A/D
VO port P3
WA RD SYNC ALE RESET Voo(Sv) VoC(Ol
"OO
Index rapist | Index register
(8)
CPU pin configuration
PO4/STBOUT
POS/OME
POBTXD
POTIRKD
PIO
Py
Pia
P13
Pia
VO port.PO
VO port.Pt
VO port,P2:
VO port.Pa:
P37
RESET
XIN
XOUT
(Ov) vss
Reset input
Clock input
Clock output
PUEEEPT
EEE
Eee
ea teehee
Proscalor
PRE 1 (8)
Prosealer
PRE 2 (8)
'Stack pointer
S@)
Prescaler
PRE 3 (6)
99
fonicol circuit
PIL@)
28)
WO por P2
P16)
VO por Pt
voc(sy)
POS/BUSTYOUT
POZCNTR
POWINT2
POOINTT
woout Watchdog timer
AorD0
VO portPO
2qRB
overflow output
AVI
agp
AgD3
Aaa
ASIDS
Asie
ArO7
'Adress latch
ALE enable output
ES
ESE
EES
i
Address
Idata bus
a
"Address bus
VO por.P4
Timer 1
TH)
Trstruction
ropistor (8)
Timer 2
12(6)
Tratruction JOME
decoder
Timer 3
13.(8)
Control instruction
PWM OUT.
Timer §
18 @)
Timer W.
we)
ONT
Timor X TX (8)
INT
XD
Busy!
out
VO pen PO
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