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PA-W1400
3) +15V generating circuit
When Q2 in the power ON/OFF circuit is turned on, the base
voltage of Q5 is increased through R11 to turn on Q5, resul-
tantly turning on Q12 and Q13. Thus the emitter voltage of
Q13is increased to about 35V.
When ZD6 cathode voltage increased to 15V or more through
L20, Q4 base voltage increases to go into saturated state,
turning off Q5, then turning off Q12 and Q13.
When
the power transistor Q13
is turned off, a counter-
electromotive force is generated by the energy stored in L20,
and the power is discharged through D8.
When ZD6 cathode voltage falls below +15V, Q4 is turned off,
turning on Q§, then turning on Q12 and Q13. By repeating the
above operation, the output is maintained at a constant level.
10s
cpu
(2) Reset signal generating block
4) -24V generating circuit
This circuit utilizes mutual inductance of L20 in the +15V
generating circuit to perform full-wave rectification with D4 ~
D7. Q8 is turned on by ZD1 (+30V) to generate -24V.
The -24V is used as the negative power for the LCD panel.
this voltage varies the contrast of the LCD.
Time lag is
provided to the negative power of the LCD and LCD control
signal for Q9, Q11, and Q10. For details of time lag, refer to
the reset circuit description.
5
4+5V generating circuit
This circuit stabilizes +5V with the Watt resistor and 5V three-
terminal regulator.
con
seo
ASE COMED
This block generates four kinds of reset signals: CPU reset signal,
gate array reset signal, floppy disk controller reset signal, and
liquid-crystal negative power reset signal.
'These signals monitor and generate +15V. The timing chart of the
power ON and OFF is shown below:
Reset timing chart
AC SW OFF
AC SW ON
DB1+PIN
(Rectitying bridge)
+15V
+5V
LCD negative
chart
PKY
PsT1
'CPU RESET
&
LCD negative power
applying signal
GATE ARRAY
RESET
When the power is supplied, the CPU reset signal is charged from
15V through R35 to C16. It is kept low until C16 + pin voltage
exceeds ZD2 VZ (+4/2V). When it exceeds VZ, the reset signal
becomes high. In the case of power OFF, the reset signal be-
comes low from high when +15V becomes about 10V.
Since the gate array reset signal must be released at least 4us in
advance to the CPU reset signal in order to take synchionization
with the CPU bus cycle, it is released in advance to the CPU.
The floppy disk controller reset signal has the opposite polarity to
the CPU.
Since the liquid-crystal power reset signal must be reeased at
least 10ms later than the gate array reset signal when the power
is supplied, and must be reset at latest simultaneously when the
power is cut off, it is reset at the same timing as the CPU reset
signal.
2. Mechanism drive block
This block is composed of the drive section of the four pulse motors;
CR (CARRIER), WH (wheel), RB (ribbon), and PF (paper eed); the
hammer solenoid drive section, and the CARRIER
origin detecting
section.
(1) Pulse motor drive section
The pulse motor is controlled by the motor drive signal which turns
'on/off the power applied to the motor and the motor excitag signal
which determines the motor rotation position.
The motor drive signal uses the gate array port for all the four
motors. The motor exciting signal uses the CPU port 2 (12~20
pin) for CR and WH and the gate array port for RB and P=.
The four sections of this block have virtually same drive circuit
composition and the same control system though the motor drive
devices are different. Therefore description is made ony on the
CARRIER motor.
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