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PA-W1400
PA-W1410/1400
Gate Array Pin Configuration
Signal function
vo
Signal function
1
VoD | — | Power supply (+5V)
— | +5V power
XOUT
| _ _ | Clock output
1_| Internal gate reset signal
XIN
1 [ Clock input
'© | Hammer drive signal
wR
1 [CPU data write timing signal
(© _| Power OFF signal
®
1_[ CPU bus oycle signal
(© | LCD scan start signal
AIS
|_| CPU address bus (Bit 15)
© | LCD data latch timing signal
AI4
|_| CPU address bus (Bit 14)
© | LCD data shift lock signal
XE]
|_| CPU address bus (Bit 13)
© | LOD drive power AC—conversion signal
22
1_| CPU address bus (Bit 12)
© | ECD data (bit 0)
Att
1_| CPU address bus (Bit 11)
© | LCD data (bit 1)
A10
1 | CPU address bus (Bit 10)
'© | LCD data (bit 2)
a9
1 | CPU address bus (Bit 9)
'© | LCD data (bit 3)
AB
1 [ CPU address bus (Bit 8)
© | Ribbon motor exciting phase signal (—B phase)
ALE
1_| Address latch enable
'© _| Ribbon motor exciting phase signal (B phase)
GND__|
— | GND
=
[GND
GND
| — | GNO
=
[GND
7
'AD7 __| VO | CPU address/Data bus (Bit7)
© _| Ribbon motor exciting phase signal (A phase)
18
Kd6__|
UO | CPU address/Data bus (Bit 6)
'© | Ribbon motor exciting phase signal (—A phase)
19
ADS__|
VO | CPU address/Data bus (Bit 5)
© | Wheel motor drive signal
20
AD4 | VO | CPU address/Data bus (Bit 4)
© | Ribbon motor drive signal
Fal
'AD3__|
VO | CPU address/Data bus (Bit 3)
© | Paper feed motor drive signal
22
'AD2___
| VO | CPU address/Data bus (Bit 2)
© | Paper feed motor exciting phase signal (A phase)
23
D1 __| VO | CPU address/Data bus (Bit 1)
© | Paper feed motor exciting phase signal (—A phase)
24
'ADO _| VO | GPU address/Data bus (Bit 0)
© | Paper feed motor exciting phase signal (B phase)
GND
[— [GND
© | Paper feed motor exciting phase signal (—B phase)
26 | SWi__|
VO | Switch inputt
© | Carriage motor drive signal
sw2__|_1_|
Switch input2
© | Floppy disk controller select signal
28 [| SW3__|
1 _| Switch inputs
(© | SOS ROM select signal
29 | swa__|_1_|
Switchinputa
(© _| 4M mask ROM select signal
30
voo | — | Switch input
— | 45V power
31
GND__|
—
[GND
—
[GND
32
PDS _| VO | Pseudo—SRAM data bus (bit 3)
© | System address bus signal (bit 14)
33
PD2__|
VO | Pseudo—SRAM data bus (bit 2)
'© | System address bus signal (bit 15)
34
PD4
1/0 | Pseudo—SRAM data bus (bit 4)
© | System address bus signal (bit 16)
35
PD1__|
VO | Pseudo—SRAM data bus (bit 1)
© | System address bus signal (bit 17)
36
PDS _| VO | Pseudo—SRAM data bus (bit 5)
(© _| System address bus signal (bit 19)
37
PDO _| VO | Pseudo—SRAM data bus (bit 0)
© | System address bus signal (bit 18)
38
PD6__|
VO | Pseudo—SRAM data bus (bité)
— | @ND
39
PD7__|
VO | Pseudo—SRAM data bus (bit7)
© _| System address bus signal (bit 7)
40
[GND | — | GND
© | System address bus signal (bit 4)
41
PAO__|
O | Pseudo—SRAM address bus (bit 0)
© | System address bus signal (bit 3)
42 | VCE | 0 | Pseudo—SRAM select signal
'© | System address bus signal (bit 5)
43
PAI__|
O | Pseudo—SRAM address bus (bit 1)
© | System address bus signal (bit 2)
44 |" PA10 | O | Pseudo—SRAM address bus (bit 10)
© | System address bus signal (bit 6)
45
PA2__|
© | Pseudo—SRAM address bus (bit 2)
© _| System address bus signal (bit 1)
46 [| VOE | 0 | Pseudo—SRAM data output allowing signal
© | Dynamic RAM low address strobe
47
PA3__|
© | Pseudo—SRAM address bus (bit 3)
© _| System address signal (bit 0)
48 | PAI? | © | Pseudo—SRAM address bus (bit 11)
(© | Dynamic RAM data write timing signal
49
PA4__|
© | Pseudo—SRAM address bus (bit 4)
© | Dynamic RAM collum address strobe
50
PAS | © | Pseudo—SRAM address bus (bit 9)
'© | Notconnected.
51
PAS__|
O | Pseudo—SRAM address bus (bit 5)
|_| LCD data reversion command signal
52
PAB__|
© | Pseudo—SRAM address bus (bit 8)
VO | System data bus (bit 6)
53
PAB
__|_O | Pseudo—SRAM address bus (bit 6)
VO [ System data bus (bit 7)
54 | PAIS | © | Pseudo—SRAM address bus (bit 13)
VO | System data bus (bit 5)
55
PA7 __| © | Pseudo—SRAM address bus (bit 7)
VO | System data bus (bit 4)
56 | WWE | 0 | Pseudo—SRAM data write timing signal
VO | System data bus (bit 2)
37 | PAI2 | © | Pseudo—SRAM address bus (bit 12)
VO | System data bus (bit 1)
58 | _pAI4 | O | Pseudo—SRAM address bus (bit 14)
VO | System data bus (bit 3)
59 | DME | | | Datamemory select signal
UO | System data bus (bit 0)
60 | and
| —[|GND
— | GND
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