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(2) RAM (Random Access Memory)
array.
and refreshes DRAM memory.
pin configurations are shown below:
DRAM Pin description
oefh
[18] vss
vor
[2
17)
04
voz [3
16] CAS
WE
[4
15]
VO3
RAS;
ae
as [6
[ra] at
as [7 |
[12] az
aa [|
[11] as
vec [9
[10] a7
Pin name
Address input
Line address strobe
Row address strobe
Column address strobe
AWE
'Address bus
(SAN: n=0~7)
Data bus
(SDn: n-0~7,
PA-W1400
DRAM (Dynamic RAM) read cycle timing chart
Address bus
(An: n=0~7)
Data bus
(Dn : ne0-7)
DRAM (Dynamic RAM) retresh cycle timing chart
Pseudo — SRAM Pin description
(TOP VIE!
= When CE is LOW and OE is LOW, tie doves
data VO dopa "data ouput erate"
Note: High: 2.4V ~ VDD.
LOW: GND ~ 0.8V
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