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INDEX#: Index signal active-low, TTL level Schmitt Trigger input. It is activated by the disk drive each time that it is sensed the diskette index hole.
TRK0#: Track 0, active-low, TTL level Schmitt Trigger input. This signal is driven low by the Disk Drive when the head is positioned over the outermost track.
WP#: Write Protected, active low TTL level Schmitt Trigger input. It is asserted by the disk drive when it reveals a disk protected from writing.
RDATA#: Read data, TTL level Schmitt Trigger input. This signal is used to carry the data read from the disk drive.
DSKCHG#: Diskette change, TTL level Schmitt Trigger input. This signal is used to report to the CPU that the diskette has been removed (the drive door has been
opened).
DRV#: Drive Select, open drain active low output. This signal is used to activate the floppy drive.
MOT#: Motor On, open drain active low output. This signal is used to activate the motor of the selected floppy drive.
HDSEL#: Head Select, open drain output used to determine which disk drive head is active. When the signal is low, then Head 0 is selected. When it is High
(open), then Head 1 is selected.
DIR#: Direction, open drain output used to set the direction of the head movement. When the signal is low, the head moves inwards, when it is high it moves
outwards.
STEP#: Step output pulse, open drain active low output. This signal is pulsed each time it is necessary to move the head to another track during a seek operation.
WDATA#: Write Data, open drain active low output. This signal is used to transfer a pre-compensation serialised data stream to the selected disk drive.
WGATE#: Write Enable, open drain active low output. This signal enables the write circuitry of the selected disk drive.
3.2.5.10
IDE signals (Connector X4 - CN7)
®
ETX
specifications foresee the presence of two IDE channels on connector X4 (CN7), and also the possibility of having two additional SATA connectors on the
board's side. However, the SOCs used on ETX-A61 only offer support to two S-ATA channels, and not to P-ATA.
For this reason, it is possible to equip the board with up to two SATA to PATA bridges; each of them can make available one PATA interface, at the expenses of
one of the external SATA connectors.
Since the P-ATA interface is derived from a SATA channel, then it will support only one device per channel. Only Master is supported. It is also
recommended to configure the IDE device as a Master.
Here following the signals related to PATA interfaces (effective availability of them depends on the module's configuration purchased):
PIDE_D[0..15]/SIDE_D[0..15]: Primary / Secondary IDE 16-bit data bus, +3.3V_S bidirectional signals.
PIDE_A[0..2]/SIDE_A[0..2]: Primary / Secondary IDE address bus, +3.3V_S bidirectional signals.
PIDE_CS1#/SIDE_CS1#: Primary / Secondary IDE Chip Select 1#, +3.3V_S active low output. They are used to select the Command Block registers on the
device found connected.
ETX-A61
ETX-A61 User Manual - Rev. First Edition: 1.0 - Last Edition: 1.2 - Author: S.B. - Reviewed by G.G. Copyright © 2017 SECO S.r.l.
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