Advertisement
IOW#: I/O Write, TTL bidirectional signal with 8k2Ω pull-up resistor to +5V_S. It is asserted to request an ISA I/O slave to accept the data currently available on the
data bus.
IOCHK#: I/O Check, TTL input and Schmitt Trigger with 4k7Ω pull-up resistor to +5V_S. This signal is driven by the ISA I/O devices to indicate that an error has
occurred, therefore requiring a NMI.
IOCHRDY: I/O Check, TTL bidirectional signal with 1kΩ pull-up resistor to +5V_S. When this signal is asserted, it means that an I/O device is requiring additional
Wait states to complete its transactions.
M16#: 16-bit Memory Chip Select, TTL bidirectional signal with 1kΩ pull-up resistor to +5V_S. This signal is activated (driven low) each time that the memory slave
device supports 16-bit accesses.
IO16#:16-bit I/O Chip Select, TTL bidirectional signal with 1kΩ pull-up resistor to +5V_S. This signal is activated (driven low) each time that the I/O device supports
16-bit I/O cycles.
REFSH#: Refresh Cycle indicator, output signal with 24mA source-sink capability, with 1kΩ pull-up resistor to +5V_S. This signal is driven low each time that a
refresh cycle is performed to prevent loss of memory contents.
NOWS#: No Wait States signal, TTL input and Schmitt Trigger with 1kΩ pull-up resistor to +5V_S. This signal is driven by the targeted I/O device each time it wants
to signal that it is able to perform the transaction in the current cycle without needing additional wait states.
MASTER#: Master signal, TTL input and Schmitt Trigger with 8k2Ω pull-up resistor to +5V_S. When this input is activated (low), then a ISA bus master is currently
driving the ISA bus. This signal is associated to a DREQ line by an ISA master when it wants take the control of the ISA Bus.
SYSCLK: ISA bus reference clock (circa 8MHz), output.
OSC: 14.318 MHz ISA Clock output.
RESETDRV: Reset, output signal with 24mA source-sink capability. It is used to reset external devices connected to ISA bus.
DREQ[0,1,2,3,5,6,7]: DMA request, TTL inputs (5V tolerant) with 8k2Ω pull-down resistors. All of these signals can be driven by external devices when they need
DMA access to the memory.
DACK[0,1,2,3,5,6,7]#: DMA request Acknowledge, 5V tolerant outputs with 24mA source-sink capability. These signals are asserted when it has been granted the
DMA access on the corresponding DMA channel.
TC: Terminal Count signal, 5V tolerant output with 24mA source-sink capability. It signals the ending of a DMA transfer.
IRQ3, IRQ4, IRQ5, IRQ6, IRQ7, IRQ9, IRQ10, IRQ11, IRQ12, IRQ14, IRQ15: Interrupt Request lines (inactive high), TTL inputs with 8k2Ω pull-up resistors to
+5V_S.
ETX-A61
ETX-A61 User Manual - Rev. First Edition: 1.0 - Last Edition: 1.2 - Author: S.B. - Reviewed by G.G. Copyright © 2017 SECO S.r.l.
33
Advertisement
