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3.2.5
Signals description
3.2.5.1
PCI Signals (connector X1 - CN6)
Since the SOCs used on ETX-A61 module doesn't offer native support for PCI bus (which is required by ETX
a PCI-express to PCI bridge (Texas Instruments
All signals are 3.3V voltage tolerant.
Here following the signals related to the PCI Bus.
PCICLK[1..4]: PCI clock outputs, for driving up to 4 external PCI slots or devices.
REQ[0..3]#: PCI Bus Request, +3.3V_S active low inputs with 10kΩ pull-up resistor. Used by external bus mastering devices to request PCI bus ownership.
GNT[0..3]#: PCI Bus Grant, +3.3V_S active low outputs. Used by the arbiter to grant the ownership of the bus.
AD[0..31]: PCI address and Data Bus lines, +3.3V_S bidirectional signals.
CBE[0..3]#: PCI Bus command and byte enable, +3.3V_S active low bidirectional signals. Multiplexed signals, used during the address phase and during the data
phase of a transaction respectively to transfer a command and enable byte lanes.
PAR: PCI bus parity bit, +3.3V_S bidirectional signal.
SERR#: System Error, +3.3V_S active low bidirectional signals with 10kΩ pull-up resistor. Used to signals system errors
GPERR#: PCI bus Parity Error, +3.3V_S active low bidirectional signals with 10kΩ pull-up resistor. Used to report data parity errors during PCI transactions.
PME#: Power Management Event, +3.3V_A active low input signal with 10kΩ pull-up resistor. Used by external devices to request a change in the device or
system power states.
LOCK#: Lock Resource, +3.3V_S active low bidirectional signals with 10kΩ pull-up resistor. This signal is used to require exclusive use of the bus to complete an
atomic operation that otherwise could require multiple transactions.
DEVSEL#: PCI Device Select, +3.3V_S active low bidirectional signals with 10kΩ pull-up resistor. This signal is driven low by any device that, during a PCI
transaction, has decoded its own address as the target of the transaction.
TRDY#: PCI Target Ready, +3.3V_S active low bidirectional signals with 10kΩ pull-up resistor. Used by the targeted device to signal that it is ready to complete the
transaction.
IRDY#: PCI Initiator Ready, +3.3V_S active low bidirectional signals with 10kΩ pull-up resistor. Used by the Bus Master to signal that it is ready to complete the
transaction.
STOP#: PCI Stop, +3.3V_S active low bidirectional signals with 10kΩ pull-up resistor. Used by the targeted device to request to the bus master to stop the current
transaction.
ETX-A61
ETX-A61 User Manual - Rev. First Edition: 1.0 - Last Edition: 1.2 - Author: S.B. - Reviewed by G.G. Copyright © 2017 SECO S.r.l.
®
XIO2001). This allows implementing a PCI bus compliant to PCI Local specifications rel. 2.3.
®
specifications), this kind of interface is realised using
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