Part 3.16: Keys; Part 3.17: Dip Switch Configuration - Alinx ZYNQ UltraScale+ AXU2CG-E User Manual

Part 3.16: Keys

There are 1 reset KEY RESET and 2 user buttons on the AXU3EG carrier
board. The reset signal is connected to the reset chip input of the core board
ACU3EG, and the user can use this reset KEY to reset the ZYNQ system. One
user KEY is connected to the MIO of the PS, and one is connected to the IO of
the PL. The reset KEY and the user KEYs are both low-level active. The
connection diagram of the user key is shown in Figure 3-16-1:
ZYNQ pin assignment of keys
Signal Name
PS_KEY1
PL_KEY1

Part 3.17: DIP Switch Configuration

There is a 4-digit DIP switch SW1 on the FPGA development board to
configure the startup mode of the ZYNQ system. The AXU3EG system
development platform supports 4 startup modes. The 4 startup modes are
JTAG debug mode, QSPI FLASH, EMMC and SD2.0 card startup mode. After
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ZYNQ Ultrascale + FPGA Board AXU2CG-E User Manual
U1
ZYNQ
Ultra
Scale+
Figure 3-16-1: Rest keys connection diagram
ZYNQ Pin Name
PS_MIO26
B43_L5_N
BANK
PS_KEY1
501
BANK
PL_KEY1
43
ZYNQ Pin Number
L15
AF12
PS KEY
PL KEY
Description
PS KEY1 Input
PL KEY1 Input
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