Alinx AX7035 User Manual page 31

Xilinx artix-7 fpga
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Figure 15-1: Segment structure of digital tube
We use a common anode digital tube. When the corresponding pin of a
certain field is low, the corresponding field is lit. When the corresponding pin of
a certain field is high, the corresponding field is not lit. The six-in-one digital
tube is a dynamic display. Due to the persistence of human vision and the
afterglow effect of the LED, although the digital tubes are not lit at the same
time, as long as the scanning speed is fast enough, the impression is a group
and stable display data, no flickering.
The same segments of the six-in-one digital tube are connected together,
a total of 8 pins, and then add 6 control signal pins, a total of 14 pins, as shown
in Figure 15-2, where DIG[0. .7] is the corresponding digital tube A, B, C, D, E,
F, G, H (ie point DP); SEL [0..5] is the six control pins of the six digital tube, is
also low level active, When the control pin is low, the corresponding digital tube
has a power supply voltage, so that the digital tube can be lit, otherwise the
corresponding digital tube cannot be lit regardless of the change of the
segment of the digital tube.
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ARTIX-7 FPGA Development Board AX7035 User Manual
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