Alinx AX7035 User Manual page 13

interface of the BANK 34 of the FPGA. The specific configuration of DDR3
SDRAM is shown in Table 6-1.
Bit Number
U4
The hardware design of DDR3 requires strict consideration of signal
integrity. We have fully considered the matching resistor/terminal resistance,
trace impedance control, and trace length control in circuit design and PCB
design to ensure high-speed and stable operation of DDR3.
Figure 6-2: The DDR3 on the FPGA Board
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ARTIX-7 FPGA Development Board AX7035 User Manual
Chip Model
MT41J128M16HA-125
Table 6-1: DDR3 SDRAM Configuration
Figure 6-1: The DDR3 DRAM Schematic
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