Intel MFSYS25V2 Specification
Technical product specification
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Summary of Contents for Intel MFSYS25V2
- Page 1 Intel Compute Module MFS5000SI ® Technical Product Specification Intel order number: E15154-007 Revision 1.4 June 2009 Enterprise Platforms and Services Division...
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Page 2: Revision History
Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. -
Page 3: Table Of Contents
Intel® Compute Module MFS5000SI TPS Table of Contents Table of Contents Introduction..........................1 Chapter Outline......................1 Intel ® Compute Module Use Disclaimer..............1 Product Overview........................2 ® Intel Compute Module MFS5000SI Feature Set ............ 2 Compute Module Layout..................3 2.2.1 Connector and Component Locations .............. - Page 4 Table of Contents Intel® Compute Module MFS5000SI TPS 4.3.4 Serial Port Connector .................... 24 4.3.5 USB 2.0 Connectors ....................25 Jumper Block Settings ......................26 Recovery Jumper Blocks ..................26 5.1.1 CMOS Clear and Password Reset Usage Procedure ........... 27 5.1.2...
- Page 5 Intel® Compute Module MFS5000SI TPS List of Figures List of Figures Figure 1. Component and Connector Location Diagram .............. 3 ® Figure 2. Intel Compute Module MFS5000SI Front Panel Layout..........4 ® Figure 3. Intel Compute Module MFS5000SI – Hole and Component Positions ......5 Figure 4.
- Page 6 List of Tables Intel® Compute Module MFS5000SI TPS List of Tables Table 1. I C Addresses for Memory Module SMB ................ 9 Table 2. Maximum 8-DIMM System Memory Configuration – x8 Single Rank ......10 Table 3. Maximum 8-DIMM System Memory Configuration – x4 Dual Rank......10 Table 4.
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Page 7: Introduction
® Intel Modular Server components require adequate airflow to cool. Intel ensures through its own chassis development and testing that when these components are used together, the fully integrated system will meet the intended thermal requirements. It is the responsibility of the system integrator who chooses not to use Intel-developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of airflow required for their specific application and environmental conditions. -
Page 8: Product Overview
Description ® ® Processors 771-pin LGA sockets supporting one or two Dual-Core or Quad-Core Intel Xeon processors 5000 sequence, with system bus speeds of 1066 MHz or 1333 MHz Memory 8 keyed DIMM slots supporting fully buffered DIMM technology (FBDIMM) memory. -
Page 9: Compute Module Layout
2.2.1 Connector and Component Locations ® The following figure shows the board layout of the Intel Compute Module MFS5000SI. Each connector and major component is identified by a number or letter. A description of each identified item is provided below the figure. -
Page 10: External I/O Connector Locations
1BProduct Overview Intel® Compute Module MFS5000SI TPS 2.2.2 External I/O Connector Locations ® The following drawing shows the layout of the external I/O components for the Intel Compute Module MFS5000SI. USB ports 1 and 2 Hard Drive Activity LED Video... -
Page 11: Compute Module Mechanical Drawings
Intel® Compute Module MFS5000SI TPS 1BProduct Overview 2.2.3 Compute Module Mechanical Drawings ® Figure 3. Intel Compute Module MFS5000SI – Hole and Component Positions Revision 1.4 Intel order number: E15154-007... -
Page 12: Functional Architecture
Compute Module MFS5000SI is based on the Intel 5000 ® Chipset Family. The chipset is designed for systems based on the Dual-Core and Quad-Core Intel ® Xeon processor 5000 sequence with system bus speeds of 667 MHz, 1066 MHz, and 1333 MHz. The chipset is made up of two main components: the Memory Controller Hub (MCH) for the host bridge and ®... -
Page 13: Intel 5000P Memory Controller Hub (Mch)
PCI Express* Ports, including the Enterprise South Bridge Interface (ESI) FBD Thermal Management SMBus Interface ® Additional information about MCH functionality can be obtained from the Intel 5000 Series Chipsets ® Server Board Family Datasheet and the Intel 5000P Memory Controller Hub External Design Specification. -
Page 14: Memory Subsystem
3.1.2.2 Common Enabling Kit (CEK) Design Support The compute module complies with Intel’s Common Enabling Kit (CEK) processor mounting and heatsink retention solution. The compute module ships with a CEK spring snapped onto the underside of the server board, beneath each processor socket. The heatsink attaches to the CEK, over the top of the processor and the thermal interface material (TIM). -
Page 15: Figure 6. Memory Layout
The MCH supports several memory RASUM (Reliability, Availability, Serviceability, Usability, and ® ® Manageability) features. These features include the Intel x4 Single Device Data Correction (Intel SDDC) for memory error detection and correction, Memory Scrubbing, Retry on Correctable Errors, Memory Built In Self Test, DIMM Sparing, and Memory Mirroring. For more information regarding these ®... -
Page 16: Table 2. Maximum 8-Dimm System Memory Configuration - X8 Single Rank
DIMM slot order: A1 and B1, C1 and D1, A2 and B2, C2 and D2. DIMMs within a given pair must be identical with respect to size, speed, and organization. Intel supported DIMM configurations for this server board are shown in the following table. Revision 1.4... - Page 17 The server board is capable of supporting a minimum of one DIMM installed. However, for system performance reasons, Intel’s recommendation is that at least 2 DIMMs be installed. The following diagram shows the recommended minimum DIMM memory configuration. Populated DIMM slots are shown in Grey.
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Page 18: Figure 7. Recommended Minimum Two-Dimm Memory Configuration
Branch 1 TP02300 Figure 7. Recommended Minimum Two-DIMM Memory Configuration Note: The server board supports single DIMM mode operation. Intel only validates and supports this configuration with a single 512MB x8 FBDIMM installed in DIMM slot A1. 3.1.3.4 Non-mirrored Mode Memory Upgrades The minimum memory upgrade increment is two DIMMs per branch. -
Page 19: Figure 8. Recommended Four-Dimm Configuration
Intel® Compute Module MFS5000SI TPS 2BFunctional Architecture Channel B Channel C Channel A Channel D Branch 0 Branch 1 TP02301 Figure 8. Recommended Four-DIMM Configuration Functionally, DIMM slots A2 and B2 could also have been populated instead of DIMM slots C1 and D1. -
Page 20: Figure 9. Single Branch Mode Sparing Dimm Configuration
The larger of the pairs {DIMM_A1, DIMM_B1} and {DIMM_A2, DIMM_B2} will be selected as the spare pair unit. ® Note: Use of identical memory is recommended with the Intel Compute Module MFS5000SI. Mixing memory type, size, speed, rank and/or vendors is not validated and is not supported with this product. - Page 21 Intel® Compute Module MFS5000SI TPS 2BFunctional Architecture ® Note: Use of identical memory is recommended with the Intel Compute Module MFS5000SI. Mixing memory type, size, speed, rank and/or vendors is not validated and is not supported with this product. Refer to section 3.1.3.2 for supported and nonsupported memory features and configuration information.
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Page 22: Intel 6321Esb I/O Controller Hub
A primary role of the Intel 6321ESB I/O Controller Hub is to provide the gateway to all PC-compatible I/O ® devices and features. The server board uses the following Intel 6321ESB I/O Controller Hub features: Dual GbE MAC Integrated Baseboard Management Controller (BMC) Universal Serial Bus 2.0 (USB) interface... -
Page 23: Serial Ata Support
Compute Module MFS5000SI design. 3.2.1.3 PE1: One x4 PCI Express* Bus Segment ® One x4 PCI Express* bus segment is directed through the Intel 6321ESB I/O Controller Hub. PCI ® Express* segment PE1 is not used in the Intel Compute Module MFS5000SI design. -
Page 24: Usb 2.0 Support
USB 2.0 ports. Two external connectors are located on the front ® edge of the server board. These two ports are the only ports of the Intel 6321ESB I/O Controller Hub that are used in the compute module design. -
Page 25: Network Interface Controller (Nic)
2BFunctional Architecture Network Interface Controller (NIC) ® Network interface support is provided from the built-in Dual GbE MAC features of the Intel 6321ESB I/O Controller Hub. These interfaces are routed over the midplane board to the Ethernet switch module in the rear of the system. -
Page 26: Table 6. Serial Header Pin-Out
2BFunctional Architecture Intel® Compute Module MFS5000SI TPS Table 6. Serial Header Pin-out Signal Name Serial Port Header Pin-out 3.5.1.2 Floppy Disk Controller The server board does not support a floppy disk controller (FDC) interface. However, the system BIOS does recognize USB floppy devices. -
Page 27: Connector / Header Locations And Pin-Outs
Intel® Compute Module MFS5000SI TPS 3BConnector / Header Locations and Pin-outs Connector / Header Locations and Pin-outs Board Connector Information The following section provides detailed information regarding all connectors, headers and jumpers on the server board. Table 7 lists all connector types available on the board and the corresponding reference designators printed on the silkscreen. -
Page 28: I/O Connector Pin-Out Definition
Modular Server Accessory AXXGBIOMEZ, a dual gigabit ® ® Ethernet card based on the Intel 82571EB. The following table details the pin-out of the Intel expansion module connector. Table 10. 120-pin I/O Mezzanine Card Connector Pin-out Signal Name Signal Name... -
Page 29: Midplane Signal Connector
Intel® Compute Module MFS5000SI TPS 3BConnector / Header Locations and Pin-outs SMB_SCL P12V PE4_MCH_RXN_C0 XE_P2_D_RXN PE4_MCH_TXP_C0 PE5_MCH_TXN_C0 PE4_MCH_RXN_C1 XE_P2_C_RXN PE4_MCH_TXP_C1 PE5_MCH_TXN_C1 PE4_MCH_RXN_C2 XE_P2_B_RXN PE4_MCH_TXP_C2 PE5_MCH_TXN_C2 PE4_MCH_RXN_C3 XE_P2_A_RXN PE4_MCH_TXP_C3 PE5_MCH_TXN_C3 CLK_100M_PCIE_N P12V WAKE_N SMB_SDA Card_ID_0 XE_P2_D_RXP PE4_MCH_TXN_C0 XE_P2_D_TXN XE_P2_C_RXP PE4_MCH_TXN_C1 XE_P2_C_TXN... -
Page 30: Serial Port Connector
3BConnector / Header Locations and Pin-outs Intel® Compute Module MFS5000SI TPS XE_P2_B_TXP SAS_P2_TXN XE_P1_D_RXP XE_P2_A_RXN XE_P2_A_TXP Fm_bl_slot_id5 XE_P1_A_RXN SMB_SCL_A XE_P1_A_TXP XE_P2_D_TXN XE_P1_B_RXN FM_BL_SLOT_ID2 XE_P1_B_TXP 12V (BL_PWR_ON) XE_P1_C_RXN reserved XE_P1_C_TXP XE_P2_B_TXN XE_P1_D_RXN reserved XE_P1_D_TXP XE_P2_A_TXN SAS_P1_RXP SMB_SDA_A XE_P1_A_TXN FM_BL_SLOT_ID0 XE_P2_C_RXP FM_BL_SLOT_ID3... -
Page 31: Usb 2.0 Connectors
Intel® Compute Module MFS5000SI TPS 3BConnector / Header Locations and Pin-outs Table 6 for the pin-out of the serial header. Table 12. Internal 9-pin Serial ‘A’ Header Pin-out (J1B1) Signal Name Description SPA_DCD DCD (carrier detect) SPA_DSR DSR (data set ready) -
Page 32: Jumper Block Settings
4BJumper Block Settings Intel® Compute Module MFS5000SI TPS Jumper Block Settings The server board has several 3-pin jumper blocks that can be used to configure, protect, or recover specific features of the server board. Pin 1 on each jumper block is denoted by an “*” or “▼”. -
Page 33: Cmos Clear And Password Reset Usage Procedure
The CMOS Clear (J1F2) and Password Reset (J4A1) recovery features are designed such that the desired operation can be achieved with minimal system down time. The usage procedure for these two ® features has changed from previous generation Intel server boards. The following procedure outlines the new usage model. -
Page 34: System Status Led - Bmc Initialization
4. Move jumper from Default operating position (pins 2-3) to “Enabled” position (pins 1-2) 5. Close the compute module 6. Reconnect AC power and power up the compute module 7. Perform standard BMC firmware update procedure through the Intel® Modular Server Control software 8. Power down and remove AC power 9. -
Page 35: Product Regulatory Requirements
Product Regulatory Requirements ® ® The Intel Compute Module MFS5000SI is evaluated as part of the Intel Modular Server System MFSYS25/MFSYS35, which requires meeting all applicable system component regulatory requirements. Refer to the ® Modular Server System MFSYS25/MFSYS35 Technical Product Specification for a complete listing of all Intel system and component regulatory requirements. -
Page 36: Appendix A: Integration And Usage Tips
Compute Module MFS5000SI ® Tested Memory List in the Intel Server Configurator Tool. For a list of Intel supported operating systems, add-in cards, and peripherals for this server ® board, see the Intel Compute Module MFS5000SI Tested Hardware and Operating System List. -
Page 37: Appendix B: Bmc Sensor Tables
Intel® Compute Module MFS5000SI TPS Appendix B: Sensor Tables Appendix B: BMC Sensor Tables Table 15 lists the sensor identification numbers and information regarding the sensor type, name, supported thresholds, and a brief description of the sensor purpose. See the Intelligent Platform Management Interface Specification, Version 2.0, for sensor and event / reading-type table information. -
Page 38: Table 15. Bmc Sensors
Appendix B: Sensor Tables Intel® Compute Module MFS5000SI TPS Sensor Rearm The rearm is a request for the event status for a sensor to be rechecked and updated upon a transition between good and bad states. Rearming the sensors can be done manually or automatically. The following abbreviations are used in the column: ‘A’: Auto rearm... - Page 39 Intel® Compute Module MFS5000SI TPS Appendix B: Sensor Tables Event / Sensor Status Name Reading Event Offset Triggers Read? Rearm Standby Type Type State 3: S3 None 4: S4 None 5: S5 / G2 None 7: G3 mechanical off None...
- Page 40 Appendix B: Sensor Tables Intel® Compute Module MFS5000SI TPS Event / Sensor Status Name Reading Event Offset Triggers Read? Rearm Standby Type Type 1: Inactive None 2: Activation Required None Sensor Hot Swap 3: Activation In Progress None Hot Swap...
- Page 41 Intel® Compute Module MFS5000SI TPS Appendix B: Sensor Tables Event / Sensor Status Name Reading Event Offset Triggers Read? Rearm Standby Type Type Processor 9Ah, Temp. Thresh. 1,2 Thermal Upper Critical Fault Ctrl % Processor Digital 9Ch, Temp. 1,2 VRD...
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Page 42: Table 16. Analog Sensor Thresholds
Appendix B: Sensor Tables Intel® Compute Module MFS5000SI TPS Table 16. Analog Sensor Thresholds Lower Non- Upper Non- Name Sensor Type Lower Critical Upper Critical Critical Critical BB Vtt Voltage 1.90V 1.5V BB +1.5V AUX Voltage 1.33V 1.65V BB +1.5V Voltage 1.33V... -
Page 43: Appendix C: Post Error Messages And Handling
Intel® Compute Module MFS5000SI TPS Appendix C: POST Error Messages and Handling Appendix C: POST Error Messages and Handling Whenever possible, the BIOS will output the current boot progress codes on the video screen. Progress codes are 32-bit quantities plus optional data. The 32-bit numbers include class, subclass, and operation information. - Page 44 Appendix C: POST Error Messages and Handling Intel® Compute Module MFS5000SI TPS Error Code Error Message Response 8305 Hot swap controller failed Major 84F2 Baseboard management controller failed to respond Major 84F3 Baseboard management controller in update mode Major 84F4...
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Page 45: Table 18. Post Error Beep Codes
Intel® Compute Module MFS5000SI TPS Appendix C: POST Error Messages and Handling Error Code Error Message Response 92A3 Serial port component was not detected. Major 92A9 Serial port component encountered a resource conflict error. Major 0xA000 TPM device not detected. -
Page 46: Appendix D: Supported Intel
® Appendix D: Supported Intel Server Chassis Intel® Compute Module MFS5000SI TPS Appendix D: Supported Intel Modular Server System ® ® The Intel Compute Module MFS5000SI is supported in the following chassis: ® Intel Modular Server System MFSYS25 ® Intel Modular Server System MFSYS35 This section provides a high-level descriptive overview of each chassis. -
Page 47: Glossary
Intel® Compute Module MFS5000SI TPS Glossary Glossary This appendix contains important terms used in the preceding chapters. For ease of use, numeric entries are listed first (for example, “82460GX”) followed by alpha entries (for example, “AGP 4x”). Acronyms are followed by non-acronyms. - Page 48 Glossary Intel® Compute Module MFS5000SI TPS Term Definition I/O and Firmware Bridge INTR Interrupt Internet Protocol IPMB Intelligent Platform Management Bus IPMI Intelligent Platform Management Interface Infrared In-Target Probe 1024 bytes Keyboard Controller Style Local Area Network Liquid Crystal Display...
- Page 49 Intel® Compute Module MFS5000SI TPS Glossary Term Definition Server Input/Output SMBus System Management Bus Server Management Interrupt (SMI is the highest priority non-maskable interrupt) Server Management Mode Server Management Software SNMP Simple Network Management Protocol To Be Determined Thermal Interface Material...
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Page 50: Reference Documents
Reference Documents Intel® Compute Module MFS5000SI TPS Reference Documents See the following documents for additional information: ® Intel 5000 Series Chipsets Server Board Family Datasheet ® Intel 5000P Memory Controller Hub External Design Specification ® Intel Enterprise South Bridge 2 (ESB2) External Design Specification ®...
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