Packet Forwarding Engine Architecture For T Series Routers; Packet Forwarding Engine Components; Data Flow - Juniper Core Router T Series Hardware Manual

Packet Forwarding Engine Architecture for T Series Routers

Packet Forwarding Engine Components

Data Flow

Copyright © 2018, Juniper Networks, Inc.
The Packet Forwarding Engines provide the Layer 2 and Layer 3 packet switching,
forwarding, and route lookup functions. The Packet Forwarding Engines are implemented
in ASICs that are physically located on the FPCs and the PICs. To ensure the efficient
movement of data, the router is designed so that ASICs on the hardware components
handle the forwarding of data.
Packet Forwarding Engine Components on page 7
Data Flow on page 7
Each Packet Forwarding Engine consists of the following components:
Layer 2/Layer 3 Packet Processing ASIC, which performs Layer 2 and Layer 3
encapsulation and decapsulation, and manages the division and reassembly of packets
within the router.
Queuing and Memory Interface ASICs, which manage the buffering of data cells in
memory and the queueing of notifications.
T Series Internet Processor, which provides the route lookup function.
Switch Interface ASICs, which extract the route lookup key and manage the flow of
data cells across the switch fabric.
Media-specific ASICs on the PICs perform control functions tailored to the PIC media
types.
To ensure the efficient movement of data, the router is designed so that ASICs on the
hardware components handle the forwarding of data. Data flows through the router in
the following sequence (see
Chapter 1: System Overview and Architecture
Figure 3 on page 8):
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