Packet Forwarding Engine Architecture For T320, T640, And T1600 Routers; Packet Forward Engine Components; Data Flow Through The T320, T640, And T1600 Router - Juniper T320 Hardware Manual

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Packet Forwarding Engine Architecture for T320, T640, and T1600 Routers

Packet Forward Engine Components

Data Flow Through the T320, T640, and T1600 Router

Copyright © 2010, Juniper Networks, Inc.
Management interface—Different levels of system management tools are provided,
including the Junos OS command-line interface (CLI), the Junos XML management
protocol, the craft interface, and SNMP.
Storage and change management—Configuration files, system images, and microcode
can be held and maintained in primary and secondary storage systems, permitting
local or remote upgrades.
Monitoring efficiency and flexibility—The router supports functions such as alarm
handling and packet counting on every port, without degrading packet-forwarding
performance.
System Architecture Description for M320, T320, T640, and T1600 Routers on page 5
Packet Forwarding Engine Architecture for T320, T640, and T1600 Routers on page 7
Packet Forward Engine Components on page 7
Data Flow Through the T320, T640, and T1600 Router on page 7
The Packet Forwarding Engines provide the Layer 2 and Layer 3 packet switching,
forwarding, and route lookup functions. The Packet Forwarding Engines are implemented
in ASICs that are physically located on the FPCs and the PICs.
Each Packet Forwarding Engine consists of the following components:
Layer 2/Layer 3 Packet Processing ASIC, which performs Layer 2 and Layer 3
encapsulation and decapsulation, and manages the division and reassembly of packets
within the router.
Queuing and Memory Interface ASICs, which manage the buffering of data cells in
memory and the queueing of notifications.
T Series Internet Processor, which provides the route lookup function.
Switch Interface ASICs, which extract the route lookup key and manage the flow of
data cells across the switch fabric.
Media-specific ASICs on the PICs that perform control functions tailored to the PIC
media types.
To ensure the efficient movement of data, the router is designed so that ASICs on the
hardware components handle the forwarding of data. Data flows through the router in
the following sequence (see Figure 3 on page 8):
Chapter 2: T320 Router System Architecture Overview
7