M10I Packet Forwarding Engine Architecture Overview; Data Flow Through The Packet Forwarding Engine - Juniper M10i Hardware Manual

M10i Multiservice Edge Router Hardware Guide

M10i Packet Forwarding Engine Architecture Overview

Data Flow Through the Packet Forwarding Engine

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The Packet Forwarding Engine performs Layer 2 and Layer 3 packet switching. It can
forward up to 15 million packets per second (Mpps) for all packet sizes. The aggregate
throughput is 4 gigabits per second (Gbps) full duplex per FPC (8 Gbps full-duplex total
throughput rate). The Packet Forwarding Engine is implemented in application-specific
integrated circuits (ASICs). It uses a centralized route lookup engine and shared memory.
The Packet Forwarding Engine architecture includes the following components:
Midplane—Transports packets, notifications, and other signals between the PICs and
the Packet Forwarding Engine (as well as other system components).
Physical Interface Card (PIC)—Physically connects the router to fiber-optic or digital
network media. A controller ASIC in each PIC performs control functions specific to
the PIC media type.
Compact Forwarding Engine Board (CFEB) or Enhanced Compact Forwarding Engine
Board (CFEB-E)—Hosts an integrated ASIC, which makes forwarding decisions,
distributes data cells to the shared memory, and directs data packets when they are
ready for transmission.
Use of ASICs promotes efficient movement of data packets through the system. Packets
flow through the Packet Forwarding Engine in the following sequence (see Figure 16 on
page 33):
Packets arrive at an incoming networking interface.
1.
The networking interface passes the packets to the CFEB or CFEB-E, where the
2.
integrated ASIC processes the packet headers, divides the packets into 64-byte data
cells, and distributes the data cells throughout the memory buffer.
The integrated ASIC on the CFEB or CFEB-E performs a route lookup for each packet
3.
and decides how to forward it.
If services are configured for the packet, the integrated ASIC reassembles the
a.
packet and passes them to the services interface.
The services interface passes the packet to the CFEB or CFEB-E, where the
b.
integrated ASIC processes the packet, divides the packet into 64-byte cells, and
distributes the data cells throughout the memory buffer.
The integrated ASIC performs a second route lookup for each packet and decides
c.
how to forward it.
The integrated ASIC notifies the outbound networking interface.
4.
The integrated ASIC reassembles data cells stored in shared memory into data packets
5.
as they are ready for transmission and passes them to the outbound networking
interface.
The outbound networking interface transmits the data packets.
6.
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