Table of Contents
Advertisement
Bit 4: Receive enable (RE)
Bit 4 selects enabling or disabling of the start of receive operation.
Bit 4
RE
Description
0
Receive operation disabled
1
Receive operation enabled
Notes: 1. Note that the RDRF, FER, PER, and OER flags in SSR are not affected when bit RE is
cleared to 0, and retain their previous state.
2. In this state, serial data reception is started when a start bit is detected in asynchronous
mode or serial clock input is detected in synchronous mode. Be sure to carry out serial
mode register (SMR) settings to decide the reception format before setting bit RE to 1.
Bit 3: Multiprocessor interrupt enable (MPIE)
Bit 3 selects enabling or disabling of the multiprocessor interrupt request. The MPIE bit setting is
only valid when asynchronous mode is selected and reception is carried out with bit MP in SMR
set to 1. The MPIE bit setting is invalid when bit COM is set to 1 or bit MP is cleared to 0.
Bit 3
MPIE
Description
0
Multiprocessor interrupt request disabled (normal receive operation)
Clearing conditions:
When data is received in which the multiprocessor bit is set to 1
1
Multiprocessor interrupt request enabled*
Note: * Receive data transfer from RSR to RDR, receive error detection, and setting of the RDRF,
FER, and OER status flags in SSR is not performed. RXI, ERI, and setting of the RDRF,
FER, and OER flags in SSR, are disabled until data with the multiprocessor bit set to 1 is
received. When a receive character with the multiprocessor bit set to 1 is received, bit
MPBR in SSR is set to 1, bit MPIE is automatically cleared to 0, and RXI and ERI requests
(when bits TIE and RIE in serial control register 3 (SCR3) are set to 1) and setting of the
RDRF, FER, and OER flags are enabled.
258
*1
(RXD pin is I/O port)
*2
(RXD pin is receive data pin)
(initial value)
(initial value)
Advertisement
Table of Contents
