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2. Interrupt enable register 1 (IENR1)
Bit
IENTA
Initial value
Read/Write
R/W
IENR1 is an 8-bit read/write register that enables or disables interrupt requests.
Bit 7: Timer A interrupt enable (IENTA)
Bit 7 enables or disables timer A overflow interrupt requests.
Bit 7
IENTA
Description
0
Disables timer A interrupt requests
1
Enables timer A interrupt requests
Bit 6: Reserved bit
Bit 6 is a readable/writable reserved bit. It is initialized to 0 by a reset.
Bit 5: Wakeup interrupt enable (IENWP)
Bit 5 enables or disables WKP
Bit 5
IENWP
Description
Disables WKP
0
Enables WKP
1
Bits 4 to 0: IRQ
to IRQ
4
Bits 4 to 0 enable or disable IRQ
Bit n
IENn
Description
Disables interrupt requests from pin IRQn
0
Enables interrupt requests from pin IRQn
1
7
6
5
—
IENWP
0
0
0
R/W
R/W
to WKP
interrupt requests.
7
0
to WKP
interrupt requests
7
0
to WKP
interrupt requests
7
0
interrupt enable (IEN4 to IEN0)
0
to IRQ
4
0
4
3
IEN4
IEN3
0
0
R/W
R/W
interrupt requests.
2
1
IEN2
IEN1
IEN0
0
0
R/W
R/W
R/W
(initial value)
(initial value)
(initial value)
(n = 4 to 0)
0
0
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