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3. Pin configuration
Table 9.19 shows the asynchronous event counter pin configuration.
Table 9.19 Pin Configuration
Name
Asynchronous event input H
Asynchronous event input L
4. Register configuration
Table 9.20 shows the register configuration of the asynchronous event counter.
Table 9.20 Asynchronous Event Counter Registers
Name
Event counter control/status register
Event counter H
Event counter L
Clock stop register 2
9.7.2
Register Descriptions
1. Event counter control/status register (ECCSR)
Bit
7
OVH
Initial Value
0
Read/Write
R/W*
Note: * Bits 7 and 6 can only be written with 0, for flag clearing.
ECCSR is an 8-bit read/write register that controls counter overflow detection, counter resetting,
and halting of the count-up function.
ECCSR is initialized to H'00 upon reset.
Abbrev.
I/O
AEVH
Input
AEVL
Input
Abbrev.
ECCSR
ECH
ECL
CKSTP2
6
5
OVL
—
0
0
R/W*
R/W
Function
Event input pin for input to event counter H
Event input pin for input to event counter L
R/W
Initial Value
R/W
H'00
R
H'00
R
H'00
R/W
H'FF
4
3
CH2
CUEH
CUEL
0
0
R/W
R/W
R/W
Address
H'FF95
H'FF96
H'FF97
H'FFFB
2
1
0
CRCH
CRCL
0
0
R/W
R/W
0
239
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