Register Descriptions - Hitachi H8/3827R Series Hardware Manual

9.5.2

Register Descriptions

1. Timer counter (TCG)
7
Bit:
TCG7
Initial value: 0
Read/Write:
—
TCG is an 8-bit up-counter which is incremented by clock input. The input clock is selected by
bits CKS1 and CKS0 in TMG.
TMIG in PMR1 is set to 1 to operate TCG as an input capture timer, or cleared to 0 to operate
TCG as an interval timer*. In input capture timer operation, the TCG value can be cleared by the
rising edge, falling edge, or both edges of the input capture input signal, according to the setting
made in TMG.
When TCG overflows from H'FF to H'00, if OVIE in TMG is 1, IRRTG is set to 1 in IRR2, and if
IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
For details of the interrupt, see 3.3, Interrupts.
TCG cannot be read or written by the CPU. It is initialized to H'00 upon reset.
Note: * An input capture signal may be generated when TMIG is modified.
2. Input capture register GF (ICRGF)
7
Bit:
ICRGF7
Initial value: 0
Read/Write: R
ICRGF is an 8-bit read-only register. When a falling edge of the input capture input signal is
detected, the current TCG value is transferred to ICRGF. If IIEGS in TMG is 1 at this time,
IRRTG is set to 1 in IRR2, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
For details of the interrupt, see 3.3, Interrupts.
To ensure dependable input capture operation, the pulse width of the input capture input signal
must be at least 2ø or 2ø
ICRGF is initialized to H'00 upon reset.
6 5
TCG6 TCG5
0 0
— —
6 5
ICRGF6 ICRGF5
0 0
R R
(when the noise canceler is not used).
SUB
4 3
TCG4 TCG3
0 0
— —
4 3
ICRGF4 ICRGF3
0 0
R R
2 1
TCG2 TCG1
0 0
— —
2 1
ICRGF2 ICRGF1
0 0
R R
0
TCG0
0
—
0
ICRGF0
0
R
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