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AD5100
Parameter
MR Pull-Up Resistance (Internal to V
RESET Hold Time Tolerance
(see
Figure 12
and
Table 8
SERIAL INTERFACES
Input Logic High (SCL, SDA)
Input Logic Low (SCL, SDA)
Output Logic High (SDA)
Output Logic Low (SDA)
Input Current
Input Capacitance
POWER SUPPLY
Supply Voltage Range
Sleep Mode Supply Current
Active Mode Supply Current
Device Power-On Threshold
Device Power-Up V
, Minimum Pulse Width
2MON
Device Power-Down Delay
1
Represent typical values at 25°C, V
2
Initial V
turn-on minimum remains as 2.2 V but the 3 V to 30 V specifications apply afterward.
2MON
3
Does not apply if V
is a digital signal.
2MON
4
V
threshold limits (see Table 6) are designed to primarily allow V
4MON
30 V. One application where this 30 V capability is useful is electronic media-oriented systems transport (eMOST) diagnostic circuits.
The RESET short-circuit current is the maximum pull-up current when RESET is driven low by a microprocessor bidirectional reset pin.
5
6
It is typical for the SCL and SDA to have resistors pulled up to V
driven directly from a low voltage logic controller without pull-up resistors.
Symbol
)
3MON
Δt
RS_HOLD
)
6
V
IH
V
IL
V
OH
V
OL
C
I
V
1MON
I
SLEEP_V1MON
I
POWER_V1MON
V
2MON, IH
V
2MON, IL
t
V2MON_PW
T
VREG_OFF_DELAY
= 12 V, and V
= 12 V.
1MON
2MON
. However, care must be taken to ensure that the minimum V
3MON
Conditions
T
= 25°C; does not apply to Code
A
0x6 and Code 0x7
T
= −40°C to +125°C; does not
A
apply to Code 0x06 and Code 0x7
External R
= 2.2 kΩ
PULL-UP
External R
= 2.2 kΩ
PULL-UP
V
= 2 V to 5.5 V
RAIL
I
= 3 mA
OL
V
= 0 V to 5.5 V
IN
V
= 0 V
2MON
V
= 12 V
2MON
V
edge triggered mode selected
2MON
V
< 0.4 V (normal mode)
2MON
2
I
C-initiated power-down
to monitor low voltage inputs. The V
4MON
Rev. A | Page 6 of 36
1
Min
Typ
37
60
−10
−17
2.0
0
0.7 × V
RAIL
0
5
6.0
2.2
4
2
10
input pin is capable of withstanding voltages up to
4MON
is met when the SCL and SDA are
IH
Max
Unit
82
kΩ
+10
%
+17
%
5.5
V
0.8
V
V
0.4
V
1
μA
pF
30
V
5
μA
2
mA
2
mA
V
0.4
V
ms
sec
μs
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