AD5100
The RESET signal is asserted and maintained except when it is
triggered by the WDI, which is described in the
section. The
RESET signal is released after the programmable
hold time, t
RS_HOLD.
As shown in Figure 17, the RESET output is push-pull
configured with the rail voltage of V
Figure 17. Reset Output
SHUTDOWN WARNING, SHDNWARN
An early shutdown warning is available for the system processor
to identify the source of failure and take appropriate action
before shutting down the external devices. Whenever the
Watchdog Input
.
3MON
V
3MON
M1
RESET
M2
voltage at V
1MON
or the voltage at V
outputs a Logic 0. If the processor sees a logic low on this pin,
the processor may issue an I
cause of failure reported in the fault detect/status register, at
Address 0x19. The processor may store the information in
external EEPROM as a record of failure history.
V
OUTPUT
4OUT
V
is an open-drain output triggered by V
4OUT
mum propagation delay, t
control over an external device or used as a monitoring signal.
Most applications using V
triggered reset function. This function is disabled by writing to
Register 0x0D[2], and it is possible to fix the value of this bit in
OTP memory.
Register 0x0D[2] = 0: enables V
RESET
•
Register 0x0D[2] = 1: prevents V
activating RESET
Rev. A | Page 20 of 36
is detected as overvoltage or undervoltage,
falls below the threshold, SHDNWARN
2MON
2
C read command to identify the
. V
can be used as a PWM
V4OUT_DELAY
4OUT
require disabling of the V
4OUT
under threshold to activate
4MON
under threshold from
4MON
with a mini-
4MON
4MON
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