Analog Devices AD5100 Manual page 18

Standard Watchdog Mode
In the default standard watchdog mode, if WDI remains either
high or low for longer than the timeout period, t
pulse is generated in an attempt to allow the system processor
to reestablish the WDI signal. The RESET pulses continue
indefinitely until a valid watchdog signal, a rising or falling edge
signal at the WDI, is received. The internal watchdog timer
clears whenever a reset is asserted. The standard WDI and
RESET timing diagrams are shown in
t
WDI
WDI
t
WD
RESET
RESET PULSE
t
WDR
t
= WATCHDOG PULSE WIDTH
WDI
t
= WATCHDOG PROGRAMMABLE TIME
WD
WDI
RESET
SHDN
Figure 14. Advanced Watchdog— SHDN Asserted After Three Trials of Resetting the Watchdog ( SHDN Released After 1 Second and the Cycle Repeats)
, a RESET
WD
Figure 13 .
t
WD
t t
WDR WDR
CONTINUOUS PULSES UNTIL WATCHDOG AWAKES
= WATCHDOG-INITIATED RESET PULSE WIDTH
Figure 13. Standard Watchdog—Pulsing Reset Until Watchdog Awakes
t
WDI
t t
WD WD
t t
WDR WDI
1 RESET PULSE 3 RESET PULSES
SHUTDOWN AT 4TH RESET PULSE
Advanced Watchdog Mode
The AD5100 can be programmed into an advanced watchdog
mode. In this mode, if WDI remains either high or low for longer
than the timeout period, t
standard mode. However, if the WDI input remains inactive after
three such RESET pulses, concurrent with the fourth RESET pulse,
SHDN is also asserted. SHDN is released after 1 second. These
actions repeat indefinitely (unless action is taken by the user), if
the processor is not responding. The advanced WDI and RESET
timing diagrams are shown in
t
WD_SHDN
RELEASE AFTER 1s
Rev. A | Page 17 of 36
AD5100
, a RESET pulse is generated, as per
WD
Figure 14 .