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AD5100
Register
Read/
Permanently
Address
Write
Settable
0x09
R/W
Yes
0x0A
R/W
Yes
0x0B
R/W
Yes
0x0C
R/W
Yes
0x0D
R/W
Yes
0x0E
R/W
Yes
0x0F
R/W
Yes
0x15
R/W
Yes
Register Name and Bit Description
V
turn-on triggered SHDN hold (t
2MON
Bit No.
Description
[2:0]
Three bits used to program V
[7:3]
Reserved
V
turn-off triggered SHDN delay (t
2MON
Bit No.
Description
[2:0]
Three bits used to program V
[7:3]
Reserved
RESET hold (t
)
RS_HOLD
Bit No.
Description
[2:0]
Three bits used to program RESET hold time
[7:3]
Reserved
Watchdog timeout (t
)
WD
Bit No.
Description
[2:0]
Three bits used to program watchdog timeout time
[7:3]
Reserved
RESET configuration
Bit No.
Description
[0]
0: RESET is active when SHDN is active
1: RESET is not active when SHDN is active
[1]
0: RESET active low
1: RESET active high
[2]
0: enables V
under threshold, causing RESET
4MON
1: prevents V
under threshold from causing RESET (for V
4MON
applications)
[3]
0: floating WDI does not activate RESET
1: floating WDI activates RESET
[7:4]
Reserved
SHDN rail voltage configuration
Bit No.
Description
[2:0]
Reserved
[3]
0: SHDN rail = V
1MON
1: SHDN rail = V
REG
[7:4]
Reserved
Watchdog mode
Bit No.
Description
[2:0]
Reserved
[3]
0: standard mode
1: advanced mode
[7:4]
Reserved
Program lock (inhibit further programming)
Bit No.
Description
[2:0]
Reserved
[3]
Reserved
[7:4]
Reserved
Rev. A | Page 24 of 36
)
2SD_HOLD
t
triggered SHDN hold time
2MON
ON
)
2SD_DELAY
t
triggered SHDN delay time
2MON
OFF
NonOTP Power-On
1
Default
0x00 (10 ms)
0x00 (100 ms)
0x00 (200 ms)
0x00 (1500 ms)
0x00
4OUT
0x00
0x00
0x00
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