Changes To Figure 25-26 - Analog Devices ADM1060 Manual

1
SCL
1 0
SDA
START BY MASTER
1
SCL
(CONTINUED)
SDA
D7
(CONTINUED)
1
SCL
SDA 1 0
START BY MASTER
1
SCL
(CONTINUED)
SDA
D7
(CONTINUED)
SCL SCL
t
HD;STA
SDA
t
BUF
P S
SMBus PROTOCOLS FOR RAM AND EEPROM
The ADM1060 contains volatile registers (RAM) and nonvola-
tile EEPROM. User RAM occupies address locations from 0x00
to 0xDF, while EEPROM occupies addresses from 0xF800 to
0xF9FF.
Data can be written to and read from both RAM and EEPROM
as single data bytes.
Data can be written only to unprogrammed EEPROM locations.
To write new data to a programmed location, it is first necessary
to erase it. EEPROM erasure cannot be done at the byte level;
1
0 1 A1 A0 R/W
ACK. BY
FRAME 1
SLAVE ADDRESS
D6 D5 D4 D3 D2 D1
FRAME 3
DATA BYTE
Figure 25. General SMBus Write Timing Diagram
1 0 1 A1 A0 R/W
ACK. BY
FRAME 1
SLAVE ADDRESS
D4
D6 D5 D3 D2 D1
FRAME 3
DATA BYTE
Figure 26. General SMBus Read Timing Diagram
t t
LOW R
t
HIGH
t
HD;DAT
Figure 27. Serial Bus Timing Diagram
9
1
D6 D4
D7 D5
SLAVE
FRAME 2
COMMAND CODE
1
9
D0 D7 D6
ACK. BY
SLAVE
1
9
D7 D6 D5 D4
SLAVE
FRAME 2
DATA BYTE
9 1
D0 D7 D6
ACK. BY
MASTER
t
F
t
SU;STA
t
SU;DAT
S
the EEPROM is arranged as 16 pages of 32 bytes, and an entire
page must be erased.
Page erasure is enabled by setting Bit 3 in register UPDCFG
(address 0x90) to 1. If this is not set, page erasure cannot occur,
even if the command byte (0xFE) is programmed across the
SMBus.
Rev. B | Page 43 of 52
9
D0
D3 D2 D1
ACK. BY
SLAVE
D5 D4 D3 D2 D1 D0
ACK. BY
FRAME N
DATA BYTE
9
D3 D2 D1 D0
ACK. BY
MASTER
D4
D5 D3 D2 D1 D0
FRAME N
DATA BYTE
t
HD;STA
t
SU;STO
ADM1060
9
STOP
BY
SLAVE
MASTER
9
STOP
NO ACK.
BY
MASTER
P