Alinx ZYNQ UltraScale+ AXU2CG-E User Manual page 41

When the network is connected to Gigabit Ethernet, the data transmission
of ZYNQ and PHY chip KSZ9031RNX is communicated through the RGMII bus,
the transmission clock is 125Mhz, and the data is sampled on the rising edge
and falling samples of the clock.
When the network is connected to 100M Ethernet, the data transmission of
ZYNQ and PHY chip KSZ9031RNX is communicated through RMII bus, and
the transmission clock is 25Mhz. Data is sampled on the rising edge and falling
samples of the clock.
ZYNQ
Ultra
Scale+
Figure 3-5-1: ZYNQ PS system and GPHY connection diagram
The Gigabit Ethernet pin assignments are as follows:
Signal Name
PHY1_TXCK
PHY1_TXD0
PHY1_TXD1
PHY1_TXD2
PHY1_TXD3
PHY1_TXCTL
PHY1_RXCK
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ZYNQ Ultrascale + FPGA Board AXU2CG-E User Manual
U1
RGMII TX
BANK
502
RGMII RX
RGMII TX
BANK
66
RGMII RX
Pin Name
PS_MIO64
PS_MIO65
PS_MIO66
PS_MIO67
PS_MIO68
PS_MIO69
PS_MIO70
U4
GPHY
(KSZ9031RNX)
U22
GPHY
(KSZ9031RNX)
Pin Number
E19 Ethernet 1 RGMII Transmit Clock
A18 Ethernet 1 Transmit data bit0
G19 Ethernet 1 Transmit data bit1
B18 Ethernet 1 Transmit data bit2
C18 Ethernet 1 Transmit data bit3
D19 Ethernet 1 Transmit Enable Signal
C19 Ethernet 1 RGMII Receive Clock
J6
J11
Description
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