Alinx ZYNQ UltraScale+ AXU2CG-E User Manual page 26

them, J29 is connected to the IO of BANK65 and BANK66, J30 is connected to
the IO of BANK25, BANK26, BANK66 and the transceiver signal of BANK505
MGT, J31 is connected to the IO of BANK24 and BANK44, J32 is connected to
the MIO, VCCO_65, VCCO_66 and +12V power supply of PS.
Among them, the IO level standard of BANK43~46 is 3.3V, and the
level standard of BANK65 and BANK66 is determined by the VCCO_65
and VCCO_66 power supply of the carrier board, but cannot exceed +1.8V;
the level standard of MIO is also 1.8V.
Pin assignment of board to board connector J29
J29 Pin Signal Name
1 B65_L2_N
3 B65_L2_P
5
7 B65_L4_N
9 B65_L4_P
11
13 B65_L1_N
15 B65_L1_P
17
19 B65_L7_P
21 B65_L7_N
23
25 B65_L15_P
27 B65_L15_N
29
31 B65_L16_P
33 B65_L16_N
35
37 B65_L14_P
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ZYNQ Ultrascale + FPGA Board AXU2CG-E User Manual
Pin Number J29 Pin
V9
U9
GND -
T8
R8
GND -
Y8
W8
GND -
L1
K1
GND -
N7
N6
GND -
P7
P6
GND -
M6
Signal Name
2 B65_L22_P
4 B65_L22_N
6 GND
8 B65_L20_P
10 B65_L20_N
12 GND
14 B65_L6_N
16 B65_L6_P
18 GND
20 B65_L17_P
22 B65_L17_N
24 GND
26 B65_L9_P
28 B65_L9_N
30 GND
32 B65_L3_N
34 B65_L3_P
36 GND
38 B65_L19_P
Pin Number
K8
K7
-
J6
H6
-
T6
R6
-
N9
N8
-
K2
J2
-
V8
U8
-
J5
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