Part 3.12: Jtag Debug Port - Alinx ZYNQ UltraScale+ AXU2CG-E User Manual

MIPI interface pin assignment
Signal Name
MIPI_CLK_P
MIPI_CLK_N
MIPI_LAN0_P
MIPI_LAN0_N
MIPI_LAN1_P
MIPI_LAN1_N
CAM_GPIO
CAM_CLK
CAM_SCL
CAM_SDA

Part 3.12: JTAG Debug Port

The JTAG interface is reserved on the AXU3EG expansion board for
downloading ZYNQ UltraScale+ programs or firmware programs to FLASH. In
order to not damage the ZYNQ UltraScale+ chip by plugging and unplugging
under power, we aded a protection diode to the JTAG signal to ensure that the
signal voltage is within the range accepted by the FPGA and avoid damage to
the ZYNQ UltraScale+ chip.
49 / 56
ZYNQ Ultrascale + FPGA Board AXU2CG-E User Manual
ZYNQ Pin Name
B65_L1_P
B65_L1_N
B65_L2_P
B65_L2_N
B65_L3_P
B65_L3_N
B43_L4_P
B43_L4_N
B43_L11_P
B43_L11_N
ZYNQ Pin
Number
W8 MIPI Input Clock Positive
Y8 MIPI Input Clock Negative
U9 MIPI Input Date LANE0 Positive
V9 MIPI Input Date LANE0 Negative
U8 MIPI Input Date LANE1 Positive
V8 MIPI Input Date LANE1 Negative
AE10 GPIO Control of Camera
AF10
Y9
AA8
Description
Clock Input of Camera
I2C Clock of Camera
I2C Data of Camera
www.alinx.com