Part 2.4: Qspi Flash - Alinx ZYNQ UltraScale+ AXU2CG-E User Manual

PS_DDR4_WE_B
PS_DDR4_CAS_B
PS_DDR4_RAS_B
PS_DDR4_ACT_B
PS_DDR4_ALERT_B
PS_DDR4_BA0
PS_DDR4_BA1
PS_DDR4_BG0
PS_DDR4_CS0_B
PS_DDR4_ODT0
PS_DDR4_PARITY
PS_DDR4_RESET_B
PS_DDR4_CLK0_P
PS_DDR4_CLK0_N
PS_DDR4_CKE0

Part 2.4: QSPI Flash

The FPGA core board ACU2CG is equipped with one 256MBit Quad-SPI
FLASH chip to form an 8-bit bandwidth data bus, the flash model is
MT25QU256ABA1EW9, which uses the 1.8V CMOS voltage standard. Due to
the non-volatile nature of QSPI FLASH, it can be used as a boot device for the
system to store the boot image of the system. These images mainly include
FPGA bit files, ARM application code, and other user data files. The specific
models and related parameters of QSPI FLASH are shown in Table 2-4-1.
Position
U5
QSPI FLASH is connected to the GPIO port of the BANK500 in the PS
section of the ZYNQ chip. In the system design, the GPIO port functions of
these PS ports need to be configured as the QSPI FLASH interface. Figure
18 / 56
ZYNQ Ultrascale + FPGA Board AXU2CG-E User Manual
PS_DDR_A14_504
PS_DDR_A15_504
PS_DDR_A16_504
PS_DDR_ACT_N_504
PS_DDR_ALERT_N_504
PS_DDR_BA0_504
PS_DDR_BA1_504
PS_DDR_BG0_504
PS_DDR_CS_N0_504
PS_DDR_ODT0_504
PS_DDR_PARITY_504
PS_DDR_RST_N_504
PS_DDR_CK0_P_504
PS_DDR_CK0_N_504
PS_DDR_CKE0_504
Model
MT25QU256ABA1EW9
Table 2-4-1: QSPI FLASH Specification
Capacity
256Mbit
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AB24
AC24
AC23
Y23
U25
V23
W22
W24
W27
U28
V24
U23
W25
W26
V28
Factory
Winbond