Part 3.10: 485 Communication Interface - Alinx ZYNQ UltraScale+ AXU2CG-E User Manual

The CAN communication pin assignments are as follows:
Signal Name
PS_CAN1_TX
PS_CAN1_RX
PS_CAN2_TX
PS_CAN2_RX

Part 3.10: 485 communication interface

There are two 485 communication interfaces on the AXU3EG carrier board.
The 485 communication port 1 is connected to the IO interface of BANK43~45
on the PL system. The 485 transceiver chip selects the MAX3485 chip from
MAXIM for the user's 485 communication service.
Figure 3-3-1 is the connection diagram of the 485 transceiver chip on the
PL side
U1
ZYNQ
Ultra
Scale+
Figure 3-3-1: 485 Communication on the PL Side
The 485 communication pins are assigned as follows:
Signal Name
PL_485_TXD1
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ZYNQ Ultrascale + FPGA Board AXU2CG-E User Manual
ZYNQ Pin Name
PS_MIO32
PS_MIO33
PS_MIO39
PS_MIO38
PL_485_RXD1
PL_485_TXD1
PL_485_DE1
BANK
43,44
45
PL_485_RXD2
PL_485_TXD2
PL_485_DE2
Pin Name
B43_L1_N
ZYNQ Pin Number
J16
L16
H19
H18
U12
RO
MAX3485
DI
/RE
DE
U2
RO
MAX3485
DI
/RE
DE
Pin Number
AH10 The 1
Description
CAN1 Receiver
CAN1 Transmitter
CAN2 Receiver
CAN2 Transmitter
B
A
B
A
Description
st
Channel 485 Transceiver
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