Analog Devices ADSP-BF609 EZ-KIT Lite Manual page 52

Software-Controlled Switches (SoftConfig)
2
Table 2-4. I C Hardware Address 0x23
GPIO MCP23017 Register Address
GPIOA
GPIOB
Page 12 of the ADSP-BF609 EZ-KIT Lite Schematic
Microchip GPIO expanders are connected to the board's ICs.
, a 10-bit bus switch, connects the link port 0 processor interface to
U41
(link port connector) when the select input signal (pin 12) is high. By
default, the select input is controlled by the boot mode switch (
U41
When the boot mode switch is set to 1 (parallel flash boot), the select line
is high, enabling the system memory controller (SMC) signals, connected
through pins
PA0-7
switch to 6 (link port boot) drives the select line low and enables the link
port 0 connection to the
The output selection, which is based on the boot mode selection, can
U41
be overridden by the Microchip (
in a case where the application needs to boot from parallel flash but then
use the link port 0 afterwards. After setting the signal high (to disable
), use to control the output of
U29 GPA3
The processor signals connected to
port to support other features. The selection line must be low in order to
disconnect the signals from the link port connector
signals to connect to the on-board parallel flash memory and EI3 connec-
tors. See ADSP-BF609 EZ-KIT Lite Schematic
2-10
0x12
0x13
and of the processor. Setting the boot mode
PB0-1
connector.
J3
U46
U41
ADSP-BF609 EZ-KIT Lite Evaluation System Manual
Default Value
0x00
0x00
shows how the three
) signal . This override is useful
GPA0
.
U41
can be disconnected from the link
. This allows the
J3
for details.
J3
).
SW2