Analog Devices ADSP-BF506F EZ-KIT Lite Manual page 78

Index
G
general-purpose IO pins (GPIO), 1-14, 2-9,
2-15
general-purpose push buttons (PB0-1),
I
installation, of this EZ-KIT Lite,
CCES, 1-3
internal flash memory interface,
IO voltage, 2-2
J
JTAG
interface, 1-15
connector (P1), 1-8, 1-15,
jumpers
diagram of locations,
JP1 (SPI flash enable),
JP2 (voltage reference select),
JP3 (VDDEXT power),
JP4 (VDDINT power),
JP5 (VDDFLASH power),
JP6 (ADC voltage ref),
L
LEDs
diagram of locations,
LED1 (reset), 2-15
LED2-4 (PF0-2), 1-14,
LED5 (power), 2-15
LED8 (reset), 2-15
license restrictions, 1-11
M
Media Instruction Set Computing (MISC),
memory map, of this EZ-KIT Lite,
Micro Signal Architecture (MSA),
I-2
1-14
1-3
1-13
2-17
2-11
2-11
2-12
2-12
2-12
2-12
2-13
2-14
2-15
ix
1-12
ix
ADSP-BF506F EZ-KIT Lite Evaluation System Manual
N
notation conventions, xviii
P
package contents, 1-2
PF0-2 (IO) signals, 2-3,
PF3-15 signals, 2-3
PG0-15 signals, 2-4
PH0-2 signals, 2-6
power
connector (P9), 1-8,
LED (LED5), 2-15
measurements, 1-17
power-on-self test (POST),
product information, xvi
programmable flag (PF)
inputs PF3-4, 1-14
push buttons (SW7-8),
R
Reduced Instruction Set Computing (RISC),
reset
LEDs (LED1), 2-15
push button (SW6),
RS-232 connector (J1),
S
schematic, of ADSP-BF506F EZ-KIT Lite,
SD connector (J3), 2-17
SPI flash memory
interface, 1-13
CS enable jumper (JP1),
SRAM memory, 1-12
See also memory map
startup, of this EZ-KIT Lite
CCES, 1-3
SW1 (UART setup) switch,
SW2 (boot mode select) switch,
2-15
2-19
1-14
2-9
ix
2-9
2-17
B-1
2-11
2-8
2-8