Analog Devices ADSP-BF506F EZ-KIT Lite Manual page 41

power-on-self test (POST) example in the ADSP-BF506F installation
directory for information on how to set up the TWI interface.
The core voltage and clock rate can be set up on the fly by the processor.
The input clock is 25 MHz. The default boot mode for the processor is
SPI flash boot. See
how to change the default boot mode.
Programmable Flags
The processor has 35 general-purpose input/output (GPIO) signals spread
across three ports (
depend on the ADSP-BF506F processor setup. The following tables show
how the programmable flag pins are used on the EZ-KIT Lite.
• PF programmable flag pins –
• PG programmable flag pins –
• PH programmable flag pins –
Table 2-1. Port F Programmable Flag Connections
Processor Pin Other Processor Function
PF0 TSCLK0/UA0_RX_ALT/TMR6/
CUD0
PF1 RSCLK0/UA0_TX_ALT/TMR5/
CDG0
PF2 DT0PRI/PWM0_BH/PPI_D8/
CZM0
PF3 TFS0/PWM0_BL/PPI_D9/
CDG0
PF4 RFS0/PWM0_CH/PPI_D10/
TACLK0
ADSP-BF506F EZ-KIT Lite Evaluation System Manual
ADSP-BF506F EZ-KIT Lite Hardware Reference
"Boot Mode Select Switch (SW2)"
, , and ). The pins are multi-functional and
PF PG PH
Table 2-1
for information on
Table 2-2
Table 2-3
EZ-KIT Lite Function
Default:
LED0
Land grid array, expansion interface II
Default:
LED1
Land grid array, expansion interface II
Default:
LED2
Land grid array, expansion interface II
Default:
PB0
Land grid array, expansion interface II
Default:
PB1
Land grid array, expansion interface II
2-3