Reference Design Of Pcie - Quectel RM510Q-GL Hardware Design

Table 16: Pin Definition of PCIe Interface
Pin No. Pin Name
55 PCIE_REFCLK_P
53 PCIE_REFCLK_M
49 PCIE_RX_P
47 PCIE_RX_M
43 PCIE_TX_P
41 PCIE_TX_M
50 PCIE_RST_N
52 PCIE_CLKREQ_N
54 PCIE_WAKE_N

4.3.3. Reference Design of PCIe

The following figure shows a reference circuit for the PCIe interface.
Host
PCIE_REFCLK_P
PCIE_REFCLK_M
PCIE_WAKE_N
PCIE_CLKREQ_N
PCIE_RST_N
Note. The voltage level VCC_IO_HOST of these three signals depend on the host side due to open drain.
RM510Q-GL_Hardware_Design
I/O
AIO
AIO
AI
AI
AO
AO
DI, OD
DO, OD
DO, OD
R4 0Ω
R5 0Ω
C5 220 nF
PCIE_TX_P
PCIE_TX_M C6 220 nF
PCIE_RX_P
PCIE_RX_M
VCC_IO_HOST
R1
10k
Figure 19: PCIe Interface Reference Circuit
Description
PCIe reference clock (+)
PCIe reference clock (-)
PCIe receive (+)
PCIe receive (-)
PCIe transmit (+)
PCIe transmit (-)
PCIe reset.
Active LOW.
PCIe clock request.
Active LOW.
PCIe wake up.
Active LOW.
PCIE_REFCLK_P
PCIE_REFCLK_M
PCIE_RX_P
PCIE_RX_M
PCIE_TX_P
PCIE_TX_M
R2 R3
10k NM/10k
PCIE_WAKE_N
PCIE_CLKREQ_N
PCIE_RST_N
R4
10k
5G Module Series
RM510Q-GL Hardware Design
Comment
100 MHz.
Require differential impedance
of 85 Ω
Require differential impedance
of 85 Ω
Require differential impedance
of 85 Ω
Open drain
Open drain
Open drain
Module
55
53
49
47
43
C1 220 nF
41
C2 220 nF
BB
54
52
50
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