Clock Generator - EUROCOM TN120T Service Manual

Schematic Diagrams

Clock Generator

Sheet 17 of 37
Clock Generator
B - 18 Clock Generator
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CLOCK GENERATOR
1.0 5VS
L2 H C B1 608 KF-121 T25
C 9 1 C10 8 C 41 9 C 42 6 C 435
10 U_ 6.3 V_ 08 1U _ 6. 3 V_ 04 1U _ 6. 3V _04 0. 1U_1 0V _X7R_04 0.1U _1 0V_X7 R_ 04
X 1 FS X8L _14 .3 18MH z
La yout not e:
4 3
PL ACE CRYS TAL WIT HIN
1 2
C 1 68
50 0 MI LS O F
C 1 67
SL G8SP 510T 2 2P_5 0V_04
22 P_ 50 V_ 04
C L K_B SEL 0
2 ,4 C L K_ BSEL 0
C L K_I C H 48
Z o=55 Oh m
1 4 C LK _I C H4 8
C L K_B SEL 1
2 ,4 C L K_ BSEL 1
C L K_B SEL 2
2 ,4 C L K_ BSEL 2
C L K_I C H 14
1 4 C LK _I C H1 4
1 4 PM_S TPC PU #
1 4 PM_S TP PCI #
PC LK_KBC
2 2 PC LK_K BC
PC LK_TP M
1 9 PC LK_TPM
3.3VS
Z o=55 Oh m
1 9 N EW _C LKR EQ#
1 4 SATA_CLKR EQ #
3.3VS
PC LK_IC H 33
1 3 PC LK _I C H3 3
10 ,11, 1 4 IC H _S MBC LK0
10 ,11, 1 4 IC H _S MBD AT0
14 C LK_PW RG D
P in- 6 1 = Pi n 13 /14 as SRC_ 0, 17/1 8 as 27 M/27 MSS
0 = Pi n 13 /14 as DOT9 6, 17/1 8 as LC D_CL K
1 = PI N 46 /47 as CPU_ ITP
P in- 7
0 = PI N 46 /47 as SRC_ 8
CR# _A( SAT A_C LKR EQ# ) - -> SRC 2/2 # - -> CL K_S ATA
CR# _B( NEW _CL KRE Q#) - -> SRC 4/4 # - -> CL K_P CIE _NE W_C ARD
CR# _H( MCH _CL KRE Q#) - -> SRC 10/ 10# - -> CLK _PC IE_ 3GP LL
CR# _G( WLA N_C LKR EQ# ) - -> SRC 9/9 # - -> CL K_P CIE _MI NI
40mi ls
C 428 C 411 C 412 C 42 2
0. 1 U_ 10V _X7R_0 4 0. 1 U_ 10V _X7R_0 4 0 .1U _1 0V_X7R_0 4 0 .1U _1 0V_X7R _04
U1
CP U1
C PU 1#
48
N C
CP U0
XTAL_I N 60
X1 C PU 0#
XTAL_O U T
59
X2 SR C4
SR C 4#
SR C3 / CR # _C
R61 2. 2K_0 4
SR C 3# / CR # _D
R68 33_ 04 FSLA 10
U SB_ 48MH z/ FSLA
SR C 11 / CR # _H
FSLB 57
F SLB /TEST_MO D E SR C 11# / CR # _G
R73 10K_04
R74 33_ 04 FSLC 62
R EF0 / FSL C /ES T_SEL SR C 7/ C R #_F
S RC 7 #/ C R #_E
37
C PU _STOP#
38
P CI _ STOP# SR C9
SR C 9#
R75 33_ 04 5
P CI 3
SR C 2/ SATA
R31 6 *33_ 04
SRC 2 #/SA TA#
R78 10K_04 4
P CI 2 /TME
SR C6
R80 *10K_0 4
SR C 6#
R82 4 75_ 1% _0 4 3
P CI 1 /C R #_ B
SR C 10
R84 4 75_ 1% _0 4 1
P CI 0 /C R #_ A S RC 10#
R76 *10K_0 4
R70 10K_04 6
P CI 4 /27_Sele ct SR C8/ ITP
S RC 8 #/ I TP#
R71 33_ 04 7
P CI F5/I TP_E N
R64 10K_04
64
S CLK 2 7MH z_N on SS/ SR C 1/ SE1
63
S DATA 27MH z_S S/S RC 1 #/ SE2
56
C K_PW R GD / PD #
S RC 0/D O TT_96
SR C0 #/D O TC _96
SLG 8S P510 T
9LPRS365
RTM875T-606-VD-GR
FSLC FSLB FSLA
CK505
Host Clock
BSEL2 BSEL1
BSEL0
Frequency
0 0 0 266 MHz
0 1 0 200 MHz
0 1 1 166 MHz
5,8, 9, 1 0, 11, 12, 13, 14, 15 , 18 ,19 ,2 0,2 1,2 2,2 3,24, 25, 29
3. 3 VS
40m ils
L 4 H CB 160 8KF -1 21T2 5
C 445 C 43 1 C 44 0 C 44 4 C 12 5 C 136
0 . 1U _ 10V_X7R _04 1 U _ 6. 3V _04 0. 1 U _10 V_X7R_0 4 0 .1U _1 0V_X7R _0 4 1 0U _6. 3V_0 8 1 U _6. 3V_ 04
C LK_MC H _ BC LK
51
C LK_MC H _B CL K 4
50 C LK_MC H _ BC LK#
C LK_MC H _B CL K# 4
C LK_CP U_BC LK
54
C LK_CP U_BC L K 2
53 C LK_CP U_BC LK#
C LK_CP U_BC L K# 2
C LK_PC IE_ N EW _CA RD
27
C LK_PC IE_N EW _C AR D 19
28 C LK_PC IE_ N EW _CA RD #
C LK_PC IE_N EW _C AR D # 19
24 C LK_PC IE_ I CH
C LK_PC IE_I CH 1 3
25 C LK_PC IE_ I CH #
C LK_PC IE_I CH # 13
33 R 40 475 _1% _04
MC H _C LKR EQ# 5
32 R 41 475 _1% _04
W LAN _C L KR EQ # 19 ,2 3
44 C LK_PC IE_ MIN I _3G
C LK_PC IE_MIN I _3 G 2 3
C LK_PC IE_ MIN I _3G #
43
C LK_PC IE_MIN I _3 G # 23
30 C LK_PC IE_ MIN I
C LK_PC IE_MIN I 19
C LK_PC IE_ MIN I #
31
C LK_PC IE_MIN I # 19
C LK_SATA
21
C LK_SATA 12
22 C LK_SATA#
C LK_SATA# 12
41 C LK_PC IE_ C R
C LK_PC IE_C R 20
40 C LK_PC IE_ C R #
C LK_PC IE_C R# 2 0
C LK_PC IE_ 3G PLL
34
C LK_PC IE_3 GP LL 5
35 C LK_PC IE_ 3G PLL#
C LK_PC IE_3 GP LL # 5
C LK_PC IE_ LAN
47
C LK_PC IE_L AN 23
46 C LK_PC IE_ LAN #
C LK_PC IE_L AN # 23
17 C LK_DR EF SS
C LK_DR EFS S 5
C LK_DR EF SS#
18
C LK_DR EFS S# 5
C LK_DR EF
13
C LK_DR EF 5
14 C LK_DR EF #
C LK_DR EF# 5
1066 MHz
800 MHz
667 MHz
2,3 , 4, 5,7 , 8, 12 , 15 , 27 1 . 05VS
3. 3 VS
SL Zdiff=100 Ohm
MS Zdiff=95 Ohm