EUROCOM TN120T Service Manual page 55

Intel Penryn 1/2
CPU ONLY SUPPORT TO 35W
U15 A
4 H_A#[35:3]
H_A#3 J4 H1
A[3]# ADS#
H_A#4 L5 E2
A[4]# BNR #
H_A#5 L4 G5
A[5]# BPRI #
H_A#6 K5
A[6]#
H_A#7 M3 H5
A[7]# DEFER #
H_A#8 N2 F21
A[8]# DRDY #
H_A#9 J1 E1
A[9]# D BSY #
H_A#10 N3
A[10] #
H_A#11 P5 F1
A[11] # BR0#
H_A#12 P2
A[12] #
H_A#13 L2 D20 H _I ER R#
A[13] # IERR #
H_A#14 P4 B3
A[14] # I NIT#
H_A#15 P1
A[15] #
H_A#16 R1 H4
A[16] # LOCK#
M1
4 H_ A D STB#0 ADSTB[ 0] #
C1 H _CPU RST#
4 H_REQ#[4: 0] RESET#
H_REQ#0 K3 F3
REQ[0] # R S[0] #
H_REQ#1 H2 F4
REQ[1] # R S[1] #
H_REQ#2 K2 G3
REQ[2] # R S[2] #
H_REQ#3 J3 G2
REQ[3] # TRDY #
H_REQ#4 L1
REQ[4] #
G6
4 H_A#[35:3]
HIT#
H_A#17 Y2 E4
A[17] # H ITM#
H_A#18 U5
A[18] #
H_A#19 R3 AD4
A[19] # BPM[0] #
H_A#20 W6 AD3
A[20] # BPM[1] #
H_A#21 U4 AD1
A[21] # BPM[2] #
H_A#22 Y5 AC4
A[22] # BPM[3] #
H_A#23 U1 AC2
A[23] # PRDY #
H_A#24 R4 AC1 H _PREQ#
A[24] # PR EQ#
H_A#25 T5 AC5 H _TCK
A[25] # TCK
H_A#26 T3 AA6 H _TDI
A[26] # TD I
H_A#27 W2 AB3
A[27] # TDO
H_A#28 W5 AB5 H _TMS
A[28] # TMS
H_A#29 Y4 AB6 H _TRST#
A[29] # TR ST#
H_A#30 U2 C20
A[30] # D BR #
H_A#31 V4
A[31] #
W3
H_A#32
A[32] #
H_A#33 AA4 TH ERM AL
A[33] #
H_A#34 AB2
A[34] #
H_A#35 AA3 D21 H _PROCHOT#
A[35] # PROC HOT#
V1 A24 H _THERMD A
4 H_ A D STB#1
ADSTB[ 1] # TH ER MDA
B25 H _THERMD C
THERMDC
A6
12 H_A20M# A20M#
A5 C7
12 H_FERR # FERR# THER MTR IP#
C4
12 H_I GN NE# I GNNE#
D5
12 H_ S TPCLK# STPCL K#
C6 H CL K
12 H _I NTR LI NT0
B4 A22
12 H _NMI LI NT1 BC LK[0 ]
A3 A21
12 H _SMI # SMI # BC LK[1 ]
M4
RSVD[ 01]
N5
RSVD[ 02]
T2
RSVD[ 03]
V3
RSVD[ 04]
B2
RSVD[ 05]
D2
RSVD[ 06]
D 22
RSVD[ 07]
D3
RSVD[ 08]
F6
RSVD[ 09]
MOLEX _47430-651 5
1. 05VS
R228 56_04 H _IER R#
R207 54.9_1%_0 4 H _PREQ#
R208 54.9_1%_0 4 H _TD I
R205 54.9_1%_0 4 H _TMS
R225 54.9_1%_0 4 H _PROCHOT#
R226 *51_1%_04 H _CPU RST#
R206 54.9_1%_0 4 H _TC K
R209 649_1%_04 H _TR ST#
Layout Note:
Route H_THERMDA and
H_THERMDC on same layer.
10 mil trace on 10 mil spacing.
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4 H_D #[63: 0]
H_ADS# 4
H_BNR # 4
H_BPRI # 4
H_DEFER# 4
H_DR DY# 4
H_DBSY# 4
H_BREQ# 4
H_I NIT# 12
H_LOCK# 4
4 H_DSTBN#0
H_CPU RST# 4 4 H_D STBP#0
H_RS# 0 4 4 H_D INV#0
H_RS# 1 4
H_RS# 2 4 4 H_D #[63: 0]
H_TRDY# 4
H_HI T# 4
H_HI TM# 4
Layout Note:
0.5" max, Zo= 55 Ohms
4 H_D S TBN#1
4 H_D S TBP # 1
4 H _DI NV#1
PM_TH RMTRIP# 5,12,26
4,17 CPU_BSEL0
4,17 CPU_BSEL1
CLK_C PU_BCL K 1 7 4,17 CPU_BSEL2
CLK_C PU_BCL K# 17
C P U _GTLREF
C336 C330
*1U _6. 3V_X5R_ 06 0.0 1U _16V_X7R_04
3.3V
3.3V
R227 C 374
R22 9
*10 0K_04 1U_6.3V_04
10K_04
U 16
1 4
V D D THERM
H_THERMDA 2 6
D+ ALERT
D 23 C
C 369
1 000P_50V_X7R_04
3 7
D- SD ATA
H_THERMDC 5 8
GND SC LK
W 83L771AWG
? ADT7421 Colay
Layout Note:
Near to Thermal
IC
U15B
H_D#[ 63:0] 4
H _D#0 E22 Y 22 H_D#32
D[ 0] # D [32]#
H _D#1 F24 AB24 H_D#33
D[ 1] # D [33]#
H _D#2 E26 V24 H_D#34
D[ 2] # D [34]#
H _D#3 G22 V26 H_D#35
D[ 3] # D [35]#
H _D#4 F23 V23 H_D#36
D[ 4] # D [36]#
H _D#5 G25 T22 H_D#37
D[ 5] # D [37]#
H _D#6 E25 U 25 H_D#38
D[ 6] # D [38]#
H _D#7 E23 U 23 H_D#39
D[ 7] # D [39]#
H _D#8 K24 Y 25 H_D#40
D[ 8] # D [40]#
H _D#9 G24 W2 2 H_D#41
D[ 9] # D [41]#
H _D#10 J 24 Y 23 H_D#42
D[ 10] # D [42]#
H _D#11 J 23 W2 4 H_D#43
D[ 11] # D [43]#
H _D#12 H 22 W2 5 H_D#44
D[ 12] # D [44]#
H _D#13 F26 AA23 H_D#45
D[ 13] # D [45]#
H _D#14 K22 AA24 H_D#46
D[ 14] # D [46]#
H _D#15 H 23 AB25 H_D#47
D[ 15] # D [47]#
J 26 Y 26
DSTBN [0] # D STBN[2]# H_DSTBN#2 4
H 26 AA26
DSTBP[ 0]# DSTBP[2]# H_DSTBP#2 4
H 25 U 22
DI NV[0]# DI NV[2]# H_DI NV#2 4
H_D#[ 63:0] 4
H _D#16 N 22 AE24 H_D#48
D[ 16] # D [48]#
H _D#17 K25 AD24 H_D#49
D[ 17] # D [49]#
H _D#18 P26 AA21 H_D#50
D[ 18] # D [50]#
H _D#19 R 23 AB22 H_D#51
D[ 19] # D [51]#
H _D#20 L23 AB21 H_D#52
D[ 20] # D [52]#
H _D#21 M24 AC26 H_D#53
D[ 21] # D [53]#
H _D#22 L22 AD20 H_D#54
D[ 22] # D [54]#
H _D#23 M23 AE22 H_D#55
D[ 23] # D [55]#
H _D#24 P25 AF23 H_D#56
D[ 24] # D [56]#
H _D#25 P23 AC25 H_D#57
D[ 25] # D [57]#
H _D#26 P22 AE21 H_D#58
D[ 26] # D [58]#
H _D#27 T24 AD21 H_D#59
D[ 27] # D [59]#
H _D#28 R 24 AC22 H_D#60
D[ 28] # D [60]#
H _D#29 L25 AD23 H_D#61
D[ 29] # D [61]#
H _D#30 T25 AF22 H_D#62
D[ 30] # D [62]#
H _D#31 N 25 AC23 H_D#63
D[ 31] # D [63]#
L26 AE25
DSTBN [1] # D STBN[3]# H_DSTBN#3 4
M26 AF24
H_DSTBP#3 4
DSTBP[ 1]# DSTBP[3]#
N 24 AC20
H_DI NV#3 4
DI NV[1]# DI NV[3]#
AD 26 R 26 COMP0
GTLREF COMP[ 0]
C 23 M IS C U 26 COMP1
TEST1 COMP[ 1]
D 25 AA1 COMP2
TEST2 COMP[ 2]
C 24 Y 1 COMP3
TEST3 COMP[ 3]
AF26
TEST4
AF1 E5
TEST5 DPRSTP# H_D P R STP# 5, 12,29
A26 B5
TEST6 DPSLP# H_D P SL P# 12
C3 D 24
TEST7 D PWR# H_D P W R# 4
CPU_BSEL0 B22 D 6
BSEL[0] PWRGOOD H_PWR GD 12
CPU_BSEL1 B23 D 7
BSEL[1] SLP# H_C P U SLP# 4
CPU_BSEL2 C 21 AE6
BSEL[2] PSI# PSI # 2 9
MOLE X_4743 0-6515
R211 1K_1%_ 04
1. 05VS
CPU_GRFE=0.7V
R212
2K_ 1%_04
Layout note:
COMP0, COMP2: 0.5" Max, Zo=27.4 Ohms
COMP1, COMP3: 0.5" Max, Zo=55
Best estimate is 18 mils wide trace for outer
layers and 14 mils wide trace if on internal
layers.
C OMP0
C OMP1
C OMP2
C OMP3
R23 R21
54.9_1%_04 27.4_1%_04
THERM_ALERT# 22
A ASD 75 1V
PM_TH RM# 14
SMD _CPU_TH E R M 22
SMC _CPU_TH E R M 22
3,4,5, 7, 8,12,15, 17, 27 1.05VS
12,13 ,1 4,15, 16, 18, 19,23 ,2 4,27, 28 3. 3V
Schematic Diagrams
Sheet 2 of 37
Intel Penryn 1/2
Ohms
R213 R 214
54.9_1%_04 27.4_1%_ 04
Intel Penryn 1/2 B - 3