Clock Generator - EUROCOM M350C Service Manual

Schematic Diagrams

Clock Generator

+3VS
+3VS
Sheet 9 of 29
Clock Generator
C406
+
47uF/6.3V_D
[28] CLKEN#
B - 10 Clock Generator (71-M3500-D02)
[3,5,6,7,8,11,12,13,14,16,17,18,19,21,23,26,27,28]
FREQUENCY SETUP TABLE
(FS2) (FS1) (FS0) CPU 3V66 66MHz OUT PCI
(MHz) (MHz) (MHz) (MHz)
0 0 0 66.66 66.66 66.66 33.33
0 0 1 100 66.66 66.66 33.33
0 1 0 200 66.66 66.66 33.33
0 1 1 133 66.66 66.66 33.33
1 0 0 66.66 66.66 66MHz_IN 66MHz_IN/2
1 0 1 100 66.66 66MHz_IN 66MHz_IN/2
1 1 0 200 66.66 66MHz_IN 66MHz_IN/2
1 1 1 133 66.66 66MHz_IN 66MHz_IN/2
Mid 0 0
Mid 0 1
Mid 1 0
Mid 1 1
L50
+3VS
HCB2012K-121T30
CT9 C87
POSCAP 10u/10V 0.1u_X7R
L49
HCB3216K-800T30
C91 C85 C81 C58 C59 C83 C80 C84 C82 C86
4.7uF 0.1u_X7R 0.1u_X7R 0.1u_X7R 0.1u_X7R 0.1u_X7R 1000PF 1000PF 1000PF 1000PF
VREG FEATURE
R343
Z1006
+3VS
*10K
R329
+3VS
R328
R352
R342 R339
R353
[13,21] SUSA#
*0
R340
0 [13] PCI_STP#
R341
[13,28] PM_STPCPU#
[8,12,14] SMB_ICHCLK
[8,12,14] SMB_ICHDATA
R330
+3VS
CONNECT TO PIN 41 GND
Iref=2.32mA
R344
R327 R44
1K
1K
L38
1 2 VDDCPU
+3VS
HCB2012K-121T30
C49 C366
10u/10V 0.1uF
L3
1 2 VDD48
+3VS
HCB2012K-121T30 F0
C50 C57
10u/10V 0.1uF C397 10p
F2
C396 10p
C88
0.1u_X7R
U4
Z1001 Z1011
26 52 RN1 1 4 4P2RX33
VDDA CPUCLKT0
VDD48 37 51 Z1012 2 3
VDD48 CPUCLKC0
Z1002 1 49 Z1013 RN2 1 4 4P2RX33
VDDREF CPUCLKT1
Z1014
48 2 3
CPUCLKC1
8
VDDPCI
Z1015
14 45 RN3 1 4 4P2RX33
VDDPCI CPUCLKT2
44 Z1016 2 3
CPUCLKC2
19
VDD3V66
32 10 Z1017
VDD3V66 PCICLK0
11 Z1018
PCICLK1
VDDCPU 46 12 Z1019
VDDCPU PCICLK2
50 13 Z1020
VDDCPU PCICLK3
Z1021
16
PCICLK4
17 Z1022
PCICLK5 T
Z1023
28 18
VTT_PWRGD# PCICLK6 T
*1K 5 F0 R364 33
CLK_ICHPCI [12]
PCICLK_F0
*1K 6 TZ1001
PCICLK_F1
*1K 7 F2 R363 *33
INT_APICCLK [12]
PCICLK_F2
0 Z1003 25
PD#
Z1004
0 34
PCI_STOP#
0 Z1005 53 43 Z1024 R326 10K
CPU_STOP# MULTSEL0/REF0
Z1025
56
REF
SMB_ICHCLK 30
SCLK
SMB_ICHDATA 29 39 Z1026
SDATA 48MHz_USB
38 Z1027
48MHz_DOT
2.7K Z1008 54
FS0
Z1007 55 C385
FS1
Z1009 40 24 Z1028
FS2 3V66_5/66MHz_IN T
10P
33 Z1029
3V66_0 T
Z1010 Z1030
42 35
IREF VCH_CLK/3V66_1
Z1031
4 21
GND 3V66_2/66MHz_OUT0
9 22 Z1032
GND 3V66_3/66MHz_OUT1
Z1033
15 23
GND 3V66_4/66MHz_OUT2 T
20
GND
475_1% 27
GND
31 2 Z1034 C390
GND X1
36
GND
41 10P
GND R350
47 3 Z1035
GND X2
1M
ICS950810/TSSOP
Y1
2 1
14.318MHZ
C384 C407
33P
33P
IF CL=18PF DEL C35,36
+3VS
DREFSSCLK_D
R41 R40 R315 R316 R39 R38
49.9_1% 49.9_1% 49.9_1% 49.9_1% 49.9_1% 49.9_1%
CLK_CPU_BCLK [3]
CLK_CPU_BCLK# [3]
CLK_ITP_CPU [3]
CLK_ITP_CPU# [3]
CLK_MCH_BCLK [6]
CLK_MCH_BCLK# [6]
R362 33
R361 33
R360 33
R359 33
R358 33
C395 C394 C393 C392 C391
10P 10P 10P 10P 10P
+3VS
R345 33
CLK_ICH14 [13]
R321 33
CLK_ICH48 [13]
R320 33
DREFCLK [5]
C368 C367
10P *10P
R357 33
CLK_ICH66 [12]
R356 33
CLK_MCH66 [5]
C389
10P
R317 33
DREFSSCLK [5]
C360 DREFSSCLK_D R311 *10
10P
C370 C369
1uF 1uF
U24
1 8
CLKIN PD# SUSA# [13,21]
2 7 SSC_SCLK *0 R36
VDD SCLK LCLKCTLA [5]
R45
SMB_ICHCLK [8,12,14]
3 6 SSC_SDATA 0
GND SDATA LCLKCTLB [5,6]
*0
R37
SMB_ICHDATA [8,12,14]
4 5 TZ1002 R46 0
CLKOUT REF_OUT
ICS91718
PCLK_LAN [18]
PCLKPCM [24]
PCLK_IO [19]
PCLK_H8 [21]
PCLK1394 [20]