Clock Generator - EUROCOM D400V Service Manual

Clock Generator

+3VS
L30
FCM2012V121
1 2
C93
C81 C504 C505 C89 C107 C108 C555
0.1UF 0.1UF 0.1UF
10UF/10V 0.1UF 0.1UF 0.1UF 0.1UF
+3VS +3VS
R436
R101
D16
10K 10K C
15,29 CPUSTP#
1SS355
VTT
C C
R437
B B Q36
R412
E Q37 E 2N3904
2N3904
10K
475_1%
L29
1 2 FCM1608K121
+3VS
C88
0.1UF
+3VS
C84 C83
10UF/10V 0.01UF
Clock Buffer (DDR)
+2.5VS
L51
1 2
FCM2012V121
C215
C220 C755 C219
10U(0805)
10U(0805) 0.01UF 0.1UF
+2.5VS
L142
1 2
FCM1608K121
C753
10U(0805)
Frequency
+3VS
Selection
R462 4.7K FS0
R463 4.7K(R) FS1
R464 4.7K(R)
FS2
6 FWDSDCLKO
R465 4.7K(R)
FS3
R466 4.7K(R)
FS4
+2.5V
+3VS
C574
0.1UF
R347 R346 +1.8VS
4.7K
4.7K
BSEL0 3
BSEL1 3
PLEASE PLACE IN COMP SIDE
AND NEAR TOGETHER
FS4 FS3 FS2 FS1 FS0
0
BSEL1 BSEL0 Function
L L
L H 0
H L
H H
Main Clock Generator
Damping Resistors
Place near to the
Clock Outputs
U21
CLOCK GEN (660)
CLK_VCC3
1
VDDREF
CPU-1
11 40 RP37 1
VDDZ CPUCLK0 CPU-2
C92 13 39 2
VDDPCI CPUCLK#0
19
VDDPCI CPU-3
0.1UF 28 44 RP36 1
VDD48 CPUCLK1 CPU-4
29 43 2
VDDAGP CPUCLK#1
42
VDDCPU
48 47 SD-1 R411
VDDSD SDCLK
12 31 AGP-1 R413
PCI_STOP# AGPCLK0
AGP-2 R414
30
AGPCLK1
5
VSSREF
ZIP-1 R451
8 9
VSSZ ZCLK0
+3VS ZIP-2 R452
18 10
VSSPCI ZCLK1
24
VSSPCI
FS3 R453
25 14
VSS48 PCICLK_F0/FS3
FS4 R454
32 15
VSSAGP PCICLK_F1/FS4
PCI-1 R455
R92 41 16
VSSCPU PCICLK0
PCI-2 R456
46 17
VSSSD PCICLK1
PCI-3
10K 20 R457
PCICLK2
PCI-4
21 R458
PCICLK3
PCI-5
22 R435
PCICLK4
PCI-6
A 45 23
CPU_STOP# PCICLK5 T
FS0 R448
2
REF0/FS0 FS1
33 3 R449
PD#/VTT_PWRGD REF1/FS1 FS2
4 R450
REF2/FS2
USB-1 R91
38 27
IREF 48M
26 MULTISEL R415
24_48M/MULTISEL
36
VDDA
SMBCLK
35
SMBCLK 7,15,25
C90 C91 SCLK
SMBDAT
34
SMBDAT 7,15,25
SDATA
0.1UF 0.01UF
37
VSSA
ICS 952011
CY 28342
Y4
1 2
MULTISEL
C82 14.318MHz
C554 C530
0.1UF
5PF 5PF
U24
CLOCK BUFFER (DDR48)
BUFFERVCC
3 2 RP64 3
VDD CLK0
12 1 4
VDD CLK#0
C708 C737 C210 23
VDD
4 RP65 4
CLK1
0.1UF 0.1UF 0.1UF 5 3
CLK#1
13 RP66 2
CLK2
14 1
CLK#2
BUF_2.5VS 10
AVDD
17 RP51 1
CLK3
C736 C750 16 2
CLK#3
0.01UF 0.1UF 24 RP50 2
CLK4
25 1
CLK#4
SMBCLK
7 26 RP49 2
SCLK CLK5
27 1
CLK#5
SMBDAT 22
SDATA
R523
19 FB_OUT
FB_OUT
FWDSDCLKO
8
CLK_IN
NEAR DDR SODIMM
FB_IN
20 28
FB_IN GND
15
GND
11
GND
9 6 By-Pass Capacitors
T NC GND
18 Place near to the Clock Buffer
T NC
21
T NC
FB_IN
ICS 93722
CY28352
CPU SDRAM ZCLK AGP PCI
0 0 1 1 100M 133M 66M 66M 33M
0 0 0 1 100M 100M 66M 66M 33M
By-Pass Capacitors
Place near to the Clock
Outputs
4 HCLK-CPU HCLK-CPU
HCLK-CPU 3
3 HCLK-CPU# HCLK-CPU#
HCLK-CPU# 3
4P2R-33
4 HCLK-661 HCLK-661
HCLK-661 5
3 HCLK-661# HCLK-661#
HCLK-661# 5
4P2R-33
22 SDCLK
T
SDCLK
22 AGPCLK
AGPCLK 5
22
AGPCLKATI
AGPCLKATI 30
AGPCLK
22
ZCLK0
ZCLK0 9
22
ZCLK1 AGPCLKATI
ZCLK1 13
33 PCICLK963
PCICLK963 13
33
PCICLK1394 ZCLK0
T
33 PCICLKPCM
PCICLKPCM 19
33 ZCLK1
PCICLKLAN
PCICLKLAN 25
PCICLKIO
33
PCICLKIO 22
33 PCICLKH8
PCICLKH8 24
PCICLK963
33 PCLK_80P
PCLK_80P 20
PCICLK1394
14.381MHZ
33 REFCLK0
REFCLK0 9
PCICLKPCM
33 REFCLK1
REFCLK1 15
33 CLKAPIC
CLKAPIC 15
PCICLKLAN
48 MHZ
22 UCLK48M
UCLK48M 16
22 SIO48M PCICLKIO
SIO48M 22
PCICLKH8
UCLK48M
4.7K
R416
DDRCLK3
2 4P2R-0
DDRCLK37
DDRCLK#3
1
DDRCLK#37
DDRCLK0
1 4P2R-0
DDRCLK07
DDRCLK#0
2
DDRCLK#07
DDRCLK2
3 4P2R-0
DDRCLK27
DDRCLK#2
4
DDRCLK#27
DDRCLK4
4 4P2R-0
DDRCLK47
DDRCLK#4
3
DDRCLK#47
DDRCLK1
3 4P2R-0
DDRCLK17
DDRCLK#1
4
DDRCLK#17
DDRCLK5
3 4P2R-0
DDRCLK57
4 DDRCLK#5
DDRCLK#57
22 FB_IN
C709 10PF(R)
Clock Generator (71-D40U0-D03) B - 5
Schematic Diagrams
R395 49.9_1%
R396 49.9_1%
49.9_1%
R393
R394 49.9_1%
C482 10PF(R)
C483 10PF(R)
C506 10PF(R)
C600 10PF(R)
C601 10PF(R)
10PF(R)
C602
C603 10PF(R)
C122 10PF(R)
C121 10PF(R)
Sheet 4 of 42
C120 10PF(R)
C119 10PF(R)
Clock Generator
C87 10PF(R)