Quectel 5G Series Hardware Design page 42

37 USB_SS_RX_P
For more details about the USB 3.1 & 2.0 specifications, please visit http://www.usb.org/home.
The USB 2.0 interface is recommended to be reserved for firmware upgrade in designs. The following
figure shows a reference circuit for USB 2.0/3.1 interface.
Host
USB_SS_TX_P
USB_SS_TX_M
USB_SS_RX_P
USB_SS_RX_M
USB_DM
USB_DP
AC coupling capacitors C3 and C4 must be placed close to the host and close to each other. C1 and C2
have been integrated inside the module, so do not place these two capacitors on your schematic and
PCB. To ensure the signal integrity of USB 2.0 data traces, R1, R2, R3 and R4 must be placed close to
the module, and the stubs must be minimized in PCB layout.
You should follow the principles below when designing for the USB interface to meet USB 3.1 and 2.0
specifications:
⚫
Route the USB signal traces as differential pairs with ground surrounded. The impedance of
differential trace of USB 2.0 and 3.1 is 90 Ω.
⚫
For USB 2.0 signal traces, the trace length should be less than 120 mm, and the differential data pair
matching should be less than 2 mm. For USB 3.1 signal traces, length matching of each differential
data pair (Tx/Rx) should be less than 0.7 mm, while the matching between Tx and Rx should be less
than 10 mm.
⚫
Do not route signal traces under crystals, oscillators, magnetic devices, PCIe and RF signal traces.
Route the USB differential traces in inner-layer of the PCB, and surround the traces with ground on
that layer and with ground planes above and below.
⚫
Junction capacitance of the ESD protection device might cause influences on USB data lines, so you
RM500Q-GL_Hardware_Design
AI USB 3.1 super-speed receive (+)
C3 220 nF
C4 220 nF
Test Points
Figure 18: Reference Circuit for USB 3.1/2.0 Interface
USB_SS_RX_P
USB_SS_RX_M
USB_SS_TX_P
USB_SS_TX_M
USB_DM
R2 0Ω
USB_DP
R1 0Ω
R3 NM-0Ω
R4 NM-0Ω
ESD
5G Module Series
RM500Q-GL Hardware Design
Module
37
35
31
C1 220 nF
29
C2 220 nF
9
7
BB
41 / 85