Appendix References - Quectel 5G Series Hardware Design

8

Appendix References

Table 47: Related Documents
SN. Document Name
[1] Quectel_RM500Q_Series_Reference_Design
[2] Quectel_RM50xQ-GL_CA&EN-DC_Features
[3] Quectel_PCIe_Card_EVB_User_Guide
Quectel_RG50xQ&RM5xxQ_Series_AT_Commands_
[4]
Manual
[5] Quectel_RM500Q_Series+IPQ8074A_Reference Design
Quectel_RG50xQ&RM5xxQ_Series_GNSS_Application_
[6]
Note
Table 48: Terms and Abbreviations
Abbreviation
BIOS
bps
BW
CHAP
COEX
CPE
CSQ
DC-DC
DC-HSDPA
RM500Q-GL_Hardware_Design
Description
Basic Input Output System
Bit Per Second
Bandwidth
Challenge-Handshake Authentication Protocol
Coexistence
Customer Premise Equipment
Cellular Signal Quality
Direct Current to Direct Current
Double Carrier-High-Speed Downlink Packet Access
5G Module Series
RM500Q-GL Hardware Design
Description
RM500Q-GL reference design
CA&ENDC combinations of
RM500Q-GL
PCIe card EVB user guide
AT commands manual for RG50xQ
series and RM5xxQ series
RM500Q+IPQ8074A reference
design
The GNSS application note for
RG50xQ and RM5xxQ series
82 / 85