Quectel 5G Series Hardware Design page 23

49 PCIE_RX_P
50 PCIE_RST_N
51 GND
52 PCIE_CLKREQ_N
53 PCIE_REFCLK_M
54 PCIE_WAKE_N
55 PCIE_REFCLK_P
2)
56 RFFE_CLK
57 GND
2)
58 RFFE_DATA
59 LAA_TX_EN*
60 WLAN_TX_EN*
61 ANTCTL1 *
62 COEX_RXD*
63 ANTCTL2*
64 COEX_TXD*
65 RFFE_VIO_1V8
1)
66 USIM1_DET
67 RESET#
68 AP2SDX_STATUS*
RM500Q-GL_Hardware_Design
(U)SIM2 card
AI PCIe receive (+)
PCIe reset.
DI, OD
Active LOW
Ground
PCIe clock request.
DO, OD
Active LOW.
AI, AO PCIe reference clock (-)
PCIe wake up.
DO, OD
Active LOW
PCIe reference clock
AI, AO
(+)
Used for external MIPI
DO, PD
IC control
Ground
Used for external MIPI
DO, PD
IC control
Notification from SDR to
DO WLAN when LTE
transmitting
Notification from WLAN
DI to SDR while
transmitting
DO, PD Antenna GPIO control
LTE/WLAN coexistence
DI, PD
receive data
DO, PD Antenna GPIO control
LTE/WLAN coexistence
DO, PD
transmit
Power supply for
2)
PO
antenna tuner
(U)SIM1 card insertion
DI, PU
detection
Reset the module.
DI
Active LOW
Status indication from
DI
AP
5G Module Series
RM500Q-GL Hardware Design
1.8/3.0 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
Maximum output
1.8 V
current: 50 mA
1.8 V
V max = 2.1 V Internally pulled
IH
V min = 1.3 V up to 1.8 V with a
IH
V max = 0.5 V 100 kΩ resistor
IL
1.8 V
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