Quectel 5G Series Hardware Design page 47

The following figure and table are PCIe turn-on timing and variables of the module.
VCC
FCPO#
RESET#
RFFE_VIO_1V8
PCIE_CLKREQ_N
PCIE_RST_N
PCIE_REFCLK
Table 18: PCIe Turn-on Timing of the Module
Symbol Min.
T 0 ms
power-on
T -
VCC-RST#
T 68 ms
turn-on
t 90 ms
FCPO#-CLKREQ#
t 100 ms
FCPO#-PERST
100 μs
T
PERST#-CLK
RM500Q-GL_Hardware_Design
Module power-on or insertion detection
System turn-on and booting
T
VCC-RST#
T > 90 ms
FCPO#-CLKREQ#
T T
power-on turn-on
Figure 21: PCIe Power-on Timing of the Module
Typ. Max.
20 ms -
33 ms -
- -
100 ms- -
- -
- -
RM500Q-GL Hardware Design
T > 100 ms
FCPO#-PERST#
T > 100 us
PERST#-CLK
Comment
Module power-on time depending on the host.
Time period between module power-on and
RESET# being driven HIGH.
Module system turn on time.
PCIe clock request.
PCIe reset.
The time period during which REFCLK is stable
before PERST# is inactive.
5G Module Series
3.7 V
≥ 1.19 V
V
IH
1.8 V
1.8 V
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